Changeset b4fa652 in mainline for boot

Timestamp:

2006-08-04T08:21:30Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b006a2c8

Parents:

d7e3fa66

Message:

Support 24bpp framebuffers with 4 pixelbytes (each pixel aligned on 32-bits).

At least on sparc64, the OpenFirmware linebytes property specifies the number
of pixels between consecutive scan lines of the display. Fix scanilne calculation,
including possible alignment.

Add note to 8bpp pixel functions pointing out drawbacks of that mode.

Location:

boot/arch/sparc64/loader

Files:

• main.c (modified) (2 diffs)
• ofwarch.c (modified) (1 diff)
• ofwarch.h (modified) (1 diff)

boot/arch/sparc64/loader/main.c

@@ -32 +32 @@
 #include "_components.h"
 #include <ofw.h>
+#include "ofwarch.h"
 #include <align.h>
 
@@ -60 +61 @@
         }
         bootinfo.screen.addr = ofw_translate(bootinfo.screen.addr);
+        /* transform scanline to bytes with respect to potential alignment */
+        bootinfo.screen.scanline = bootinfo.screen.scanline*bpp2align[bootinfo.screen.bpp >> 3];
         
         if (!ofw_keyboard(&bootinfo.keyboard))
                 printf("Error: unable to get keyboard properties\n");
-        
+
         printf("\nDevice statistics\n");
         printf(" memory: %dM\n", bootinfo.memmap.total>>20);

boot/arch/sparc64/loader/ofwarch.c

@@ -36 +36 @@
 #include <printf.h>
 
+int bpp2align[] = {
+        [0] = 0,                /** Invalid bpp. */
+        [1] = 1,                /** 8bpp is not aligned. */
+        [2] = 2,                /** 16bpp is naturally aligned. */
+        [3] = 4,                /** 24bpp is aligned on 4 byte boundary. */
+        [4] = 4,                /** 32bpp is naturally aligned. */
+};
+
 void write(const char *str, const int len)
 {

boot/arch/sparc64/loader/ofwarch.h

@@ -33 +33 @@
 #define OFW_SIZE_CELLS          2
 
+extern int bpp2align[];
+
 #endif