Changeset b1011dae in mainline for kernel/arch/arm32/include

Timestamp:

2013-01-24T21:18:18Z (13 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

077b9172

Parents:

5e761f3 (diff), c124dce3 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge changes from jan.vesely/helenos/arm

Location:

kernel/arch/arm32/include

Files:

• asm.h (modified) (1 diff)
• barrier.h (modified) (2 diffs)
• cache.h (added)
• cp15.h (added)
• cpu.h (modified) (2 diffs)
• cycle.h (modified) (2 diffs)
• mm/frame.h (modified) (1 diff)
• mm/page.h (modified) (1 diff)
• mm/page_fault.h (modified) (1 diff)
• regutils.h (modified) (1 diff)
• security_ext.h (added)

kernel/arch/arm32/include/asm.h

@@ -43 +43 @@
 #include <trace.h>
 
-/** No such instruction on old ARM to sleep CPU.
+/** CPU specific way to sleep cpu.
  *
  * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
  * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
  * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
+ * ARM926EJ-S uses the same coprocessor instruction as ARM920T. See ARM926EJ-S
+ * chapter 2.3.8 p.2-22 (52 in the PDF)
+ *
+ * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
+ * reference manual for armv4/5 CP15 implementation is mandatory only for
+ * armv6+.
  */
 NO_TRACE static inline void cpu_sleep(void)
 {
-#ifdef PROCESSOR_armv7_a
-        asm volatile ( "wfe" :: );
-#elif defined(MACHINE_gta02)
-        asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
+#ifdef PROCESSOR_ARCH_armv7_a
+        asm volatile ( "wfe" );
+#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
+        asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
 #endif
 }

kernel/arch/arm32/include/barrier.h

@@ -37 +37 @@
 #define KERN_arm32_BARRIER_H_
 
-/*
- * TODO: implement true ARM memory barriers for macros below.
- */
+#ifdef KERNEL
+#include <arch/cp15.h>
+#else
+#include <libarch/cp15.h>
+#endif
+
 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
+#if defined PROCESSOR_ARCH_armv7_a
+/* ARMv7 uses instructions for memory barriers see ARM Architecture reference
+ * manual for details:
+ * DMB: ch. A8.8.43 page A8-376
+ * DSB: ch. A8.8.44 page A8-378
+ * See ch. A3.8.3 page A3-148 for details about memory barrier implementation
+ * and functionality on armv7 architecture.
+ */
+#define memory_barrier()  asm volatile ("dmb" ::: "memory")
+#define read_barrier()    asm volatile ("dsb" ::: "memory")
+#define write_barrier()   asm volatile ("dsb st" ::: "memory")
+#define inst_barrier()    asm volatile ("isb" ::: "memory")
+#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL
+/*
+ * ARMv6 introduced user access of the following commands:
+ * - Prefetch flush
+ * - Data synchronization barrier
+ * - Data memory barrier
+ * - Clean and prefetch range operations.
+ * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
+ */
+/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
+ * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
+ * CP15 implementation is mandatory only for armv6+.
+ */
+#define memory_barrier()  CP15DMB_write(0)
+#define read_barrier()    CP15DSB_write(0)
+#define write_barrier()   read_barrier()
+#define inst_barrier()    CP15ISB_write(0)
+#else
+/* Older manuals mention syscalls as a way to implement cache coherency and
+ * barriers. See for example ARM Architecture Reference Manual Version D
+ * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
+ */
+// TODO implement on per PROCESSOR basis or via syscalls
 #define memory_barrier()  asm volatile ("" ::: "memory")
 #define read_barrier()    asm volatile ("" ::: "memory")
 #define write_barrier()   asm volatile ("" ::: "memory")
+#define inst_barrier()    asm volatile ("" ::: "memory")
+#endif
 
 /*
@@ -62 +102 @@
  */
 
-/* Available on both all supported arms,
+#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
+/* Available on all supported arms,
  * invalidates entire ICache so the written value does not matter. */
-#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
-#define smc_coherence_block(a, l) smc_coherence(a)
+//TODO might be PL1 only on armv5-
+#define smc_coherence(a) \
+do { \
+        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
+        write_barrier();               /* Wait for completion */\
+        ICIALLU_write(0);              /* Flush ICache */\
+        inst_barrier();                /* Wait for Inst refetch */\
+} while (0)
+/* @note: Cache type register is not available in uspace. We would need
+ * to export the cache line value, or use syscall for uspace smc_coherence */
+#define smc_coherence_block(a, l) \
+do { \
+        for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
+                smc_coherence(addr); \
+} while (0)
+#else
+#define smc_coherence(a)
+#define smc_coherence_block(a, l)
+#endif
 
 

kernel/arch/arm32/include/cpu.h

@@ -40 +40 @@
 #include <arch/asm.h>
 
+enum {
+        ARM_MAX_CACHE_LEVELS = 7,
+};
 
 /** Struct representing ARM CPU identification. */
@@ -57 +60 @@
         /** Revision number. */
         uint32_t rev_num;
+
+        struct {
+                unsigned ways;
+                unsigned sets;
+                unsigned line_size;
+                unsigned way_shift;
+                unsigned set_shift;
+        } dcache[ARM_MAX_CACHE_LEVELS];
+        unsigned dcache_levels;
 } cpu_arch_t;
 

kernel/arch/arm32/include/cycle.h

@@ -38 +38 @@
 
 #include <trace.h>
+#include <arch/cp15.h>
 
 /** Return count of CPU cycles.
@@ -48 +49 @@
 NO_TRACE static inline uint64_t get_cycle(void)
 {
+#ifdef PROCESSOR_ARCH_armv7_a
+        if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) ==
+            ID_PFR1_GEN_TIMER_EXT) {
+            uint32_t low = 0, high = 0;
+            asm volatile( "MRRC p15, 0, %[low], %[high], c14": [low]"=r"(low), [high]"=r"(high));
+           return ((uint64_t)high << 32) | low;
+        } else {
+                return (uint64_t)PMCCNTR_read() * 64;
+        }
+#endif
         return 0;
 }

kernel/arch/arm32/include/mm/frame.h

@@ -47 +47 @@
 
 #ifdef MACHINE_gta02
+
+#define PHYSMEM_START_ADDR       0x30008000
 #define BOOT_PAGE_TABLE_ADDRESS  0x30010000
+
 #elif defined MACHINE_beagleboardxm
+
+#define PHYSMEM_START_ADDR       0x80000000
 #define BOOT_PAGE_TABLE_ADDRESS  0x80008000
+
 #elif defined MACHINE_beaglebone
+
+#define PHYSMEM_START_ADDR       0x80000000
 #define BOOT_PAGE_TABLE_ADDRESS  0x80008000
+
 #else
+
+#define PHYSMEM_START_ADDR       0x00000000
 #define BOOT_PAGE_TABLE_ADDRESS  0x00008000
+
 #endif
 
 #define BOOT_PAGE_TABLE_START_FRAME     (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH)
 #define BOOT_PAGE_TABLE_SIZE_IN_FRAMES  (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH)
-
-#ifdef MACHINE_gta02
-#define PHYSMEM_START_ADDR      0x30008000
-#elif defined MACHINE_beagleboardxm
-#define PHYSMEM_START_ADDR      0x80000000
-#elif defined MACHINE_beaglebone
-#define PHYSMEM_START_ADDR      0x80000000
-#else
-#define PHYSMEM_START_ADDR      0x00000000
-#endif
 
 extern void frame_low_arch_init(void);

kernel/arch/arm32/include/mm/page.h

@@ -129 +129 @@
         set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
 
-#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
+#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
 #include "page_armv6.h"
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
 #include "page_armv4.h"
 #else

kernel/arch/arm32/include/mm/page_fault.h

@@ -42 +42 @@
 /** Decribes CP15 "fault status register" (FSR).
  *
- * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743).
+ * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
+ * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
+ * the architecture. A write flag (bit[11] of the DFSR) has also been
+ * introduced."
+ * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
+ *
+ * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). for FSR info
  */
 typedef union {

kernel/arch/arm32/include/regutils.h

@@ -41 +41 @@
 #define STATUS_REG_MODE_MASK         0x1f
 
-/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
- * Manual ARMv7-A and ARMv7-R edition, page 1687 */
-#define CP15_R1_MMU_EN            (1 << 0)
-#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
-#define CP15_R1_CACHE_EN          (1 << 2)
-#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
-#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
-#define CP15_R1_SWAP_EN           (1 << 10)
-#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
-#define CP15_R1_INST_CACHE_EN     (1 << 12)
-#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
-#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
-#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
-#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
-#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
-#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
-#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
-#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
-#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
-#define CP15_R1_NMFI_EN           (1 << 27)
-#define CP15_R1_TEX_REMAP_EN      (1 << 28)
-#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
-#define CP15_R1_THUMB_EXC_EN      (1 << 30)
-
 /* ARM Processor Operation Modes */
-#define USER_MODE        0x10
-#define FIQ_MODE         0x11
-#define IRQ_MODE         0x12
-#define SUPERVISOR_MODE  0x13
-#define ABORT_MODE       0x17
-#define UNDEFINED_MODE   0x1b
-#define SYSTEM_MODE      0x1f
-
+enum {
+        USER_MODE = 0x10,
+        FIQ_MODE = 0x11,
+        IRQ_MODE = 0x12,
+        SUPERVISOR_MODE = 0x13,
+        MONITOR_MODE = 0x16,
+        ABORT_MODE = 0x17,
+        HYPERVISOR_MODE = 0x1a,
+        UNDEFINED_MODE = 0x1b,
+        SYSTEM_MODE = 0x1f,
+        MODE_MASK = 0x1f,
+};
 /* [CS]PRS manipulation macros */
 #define GEN_STATUS_READ(nm, reg) \