Changeset b1011dae in mainline for boot/arch/arm32/src

Timestamp:

2013-01-24T21:18:18Z (12 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

077b9172

Parents:

5e761f3 (diff), c124dce3 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge changes from jan.vesely/helenos/arm

Location:

boot/arch/arm32/src

Files:

• asm.S (modified) (1 diff)
• main.c (modified) (5 diffs)
• mm.c (modified) (2 diffs)

boot/arch/arm32/src/asm.S

@@ -61 +61 @@
         #
 
-#if defined(MACHINE_gta02)
+        #
+        # r0 is kernel entry point
+        # r1 is pointer to the bootinfo structure
 
 #define CP15_C1_IC              12
+#define CP15_C1_BP              11
 #define CP15_C1_DC              2
-#define CP15_C7_SEG_SHIFT       5
-#define CP15_C7_SEG_SIZE        3
-#define CP15_C7_IDX_SHIFT       26
-
         # Disable I-cache and D-cache before the kernel is started.
         mrc     p15, 0, r4, c1, c0, 0
         bic     r4, r4, #(1 << CP15_C1_DC)
         bic     r4, r4, #(1 << CP15_C1_IC)
+        bic     r4, r4, #(1 << CP15_C1_BP)
         mcr     p15, 0, r4, c1, c0, 0
+
+        
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        dsb
+#else
+        #cp15 dsb, r4 is ignored (should be zero)
+        mcr p15, 0, r4, c7, c10, 4
+#endif
+        
+        # Clean ICache and BPredictors, r4 ignored (SBZ)
+        mcr p15, 0, r4, c7, c5, 0
+        nop
+
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        isb
+        nop
+#else
+        # cp15 isb
+        mcr p15, 0, r4, c7, c5, 4
+        nop
+#endif
+        
+#TODO:This should not be necessary
+
+#if defined(MACHINE_gta02)
+
+#define CP15_C7_SEG_SHIFT       5
+#define CP15_C7_SEG_SIZE        3
+#define CP15_C7_IDX_SHIFT       26
 
         # Now clean D-cache to guarantee coherency between I-cache and D-cache.

boot/arch/arm32/src/main.c

@@ -50 +50 @@
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
 
+extern void *bdata_start;
+extern void *bdata_end;
+
+
+static inline void invalidate_icache(void)
+{
+        /* ICIALLU Invalidate entire ICache */
+        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
+}
+
+static inline void invalidate_dcache(void *address, size_t size)
+{
+        const uintptr_t addr = (uintptr_t)address;
+        /* DCIMVAC - invalidate by address to the point of coherence */
+        for (uintptr_t a = addr; a < addr + size; a += 4) {
+                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
+        }
+}
+
+static inline void clean_dcache_poc(void *address, size_t size)
+{
+        const uintptr_t addr = (uintptr_t)address;
+        /* DCCMVAC - clean by address to the point of coherence */
+        for (uintptr_t a = addr; a < addr + size; a += 4) {
+                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
+        }
+}
+
 static bootinfo_t bootinfo;
 
 void bootstrap(void)
 {
+        /* Make sure  we run in memory code when caches are enabled,
+         * make sure we read memory data too. This part is ARMv7 specific as
+         * ARMv7 no longer invalidates caches on restart.
+         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
+        invalidate_icache();
+        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
+
+        /* Enable MMU and caches */
         mmu_start();
         version_print();
         
+        printf("Boot data: %p -> %p\n", &bdata_start, &bdata_end);
         printf("\nMemory statistics\n");
         printf(" %p|%p: bootstrap stack\n", &boot_stack, &boot_stack);
@@ -64 +101 @@
             (void *) PA2KA(BOOT_OFFSET), (void *) BOOT_OFFSET);
         
-        size_t i;
-        for (i = 0; i < COMPONENTS; i++)
+        for (size_t i = 0; i < COMPONENTS; i++) {
                 printf(" %p|%p: %s image (%u/%u bytes)\n", components[i].start,
                     components[i].start, components[i].name, components[i].inflated,
                     components[i].size);
+                invalidate_dcache(components[i].start, components[i].size);
+        }
         
         void *dest[COMPONENTS];
@@ -74 +112 @@
         size_t cnt = 0;
         bootinfo.cnt = 0;
-        for (i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
+        for (size_t i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
                 top = ALIGN_UP(top, PAGE_SIZE);
                 
@@ -94 +132 @@
         printf("\nInflating components ... ");
         
-        for (i = cnt; i > 0; i--) {
+        for (size_t i = cnt; i > 0; i--) {
                 void *tail = components[i - 1].start + components[i - 1].size;
                 if (tail >= dest[i - 1]) {
@@ -106 +144 @@
                 int err = inflate(components[i - 1].start, components[i - 1].size,
                     dest[i - 1], components[i - 1].inflated);
-                
                 if (err != EOK) {
                         printf("\n%s: Inflating error %d\n", components[i - 1].name, err);
                         halt();
                 }
+                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
         }
         
         printf(".\n");
         
-        printf("Booting the kernel... \n");
+        void *kernel_end = (void *) PA2KA(BOOT_OFFSET + components[0].inflated);
+        printf("Booting the kernel...\n");
         jump_to_kernel((void *) PA2KA(BOOT_OFFSET), &bootinfo);
 }

boot/arch/arm32/src/mm.c

@@ -66 +66 @@
         else
                 return 1;
-#else
+#elif defined MACHINE_beagleboardxm
+        const unsigned long address = section << PTE_SECTION_SHIFT;
+        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
+                return 1;
+#endif
         return 0;
-#endif
 }
 
@@ -129 +132 @@
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#ifdef PROCESSOR_armv7_a
-                /* Mask to enable paging, caching */
-                "ldr r1, =0x00000005\n"
-#else
-#ifdef MACHINE_gta02
-                /* Mask to enable paging (bit 0),
-                   D-cache (bit 2), I-cache (bit 12) */
-                "ldr r1, =0x00001005\n"
-#else
-                /* Mask to enable paging */
-                "ldr r1, =0x00000001\n"
-#endif
-#endif
+                /* Enable ICache, DCache, BPredictors and MMU,
+                 * we disable caches before jumping to kernel
+                 * so this is safe for all archs.
+                 */
+                "ldr r1, =0x00001805\n"
+                
                 "orr r0, r0, r1\n"