Changes in uspace/drv/pciintel/pci.c [99e6bfb:af6b5157] in mainline
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uspace/drv/pciintel/pci.c (modified) (7 diffs)
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uspace/drv/pciintel/pci.c
r99e6bfb raf6b5157 51 51 #include <ipc/devman.h> 52 52 #include <ipc/dev_iface.h> 53 #include <ipc/irc.h>54 #include <ipc/ns.h>55 #include <ipc/services.h>56 #include <sysinfo.h>57 53 #include <ops/hw_res.h> 58 54 #include <device/hw_res.h> 59 55 #include <ddi.h> 60 56 #include <libarch/ddi.h> 61 #include <pci_dev_iface.h>62 57 63 58 #include "pci.h" … … 88 83 static bool pciintel_enable_interrupt(ddf_fun_t *fnode) 89 84 { 90 /* This is an old ugly way, copied from ne2000 driver */ 91 assert(fnode); 92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data; 93 94 sysarg_t apic; 95 sysarg_t i8259; 96 int irc_phone = -1; 97 int irc_service = 0; 98 99 if ((sysinfo_get_value("apic", &apic) == EOK) && (apic)) { 100 irc_service = SERVICE_APIC; 101 } else if ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259)) { 102 irc_service = SERVICE_I8259; 103 } 104 105 if (irc_service) { 106 while (irc_phone < 0) 107 irc_phone = service_connect_blocking(irc_service, 0, 0); 108 } else { 109 return false; 110 } 111 112 size_t i; 113 for (i = 0; i < dev_data->hw_resources.count; i++) { 114 if (dev_data->hw_resources.resources[i].type == INTERRUPT) { 115 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq; 116 async_msg_1(irc_phone, IRC_ENABLE_INTERRUPT, irq); 117 } 118 } 119 120 async_hangup(irc_phone); 121 return true; 122 } 123 124 static int pci_config_space_write_16(ddf_fun_t *fun, uint32_t address, uint16_t data) 125 { 126 if (address > 254) 127 return EINVAL; 128 pci_conf_write_16(PCI_FUN(fun), address, data); 129 return EOK; 130 } 131 85 /* TODO */ 86 87 return false; 88 } 132 89 133 90 static hw_res_ops_t pciintel_hw_res_ops = { … … 136 93 }; 137 94 138 static pci_dev_iface_t pci_dev_ops = { 139 .config_space_read_8 = NULL, 140 .config_space_read_16 = NULL, 141 .config_space_read_32 = NULL, 142 .config_space_write_8 = NULL, 143 .config_space_write_16 = &pci_config_space_write_16, 144 .config_space_write_32 = NULL 145 }; 146 147 static ddf_dev_ops_t pci_fun_ops = { 148 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops, 149 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops 150 }; 95 static ddf_dev_ops_t pci_fun_ops; 151 96 152 97 static int pci_add_device(ddf_dev_t *); … … 342 287 /* Get the value of the BAR. */ 343 288 val = pci_conf_read_32(fun, addr); 344 345 #define IO_MASK (~0x3)346 #define MEM_MASK (~0xf)347 289 348 290 io = (bool) (val & 1); 349 291 if (io) { 350 292 addrw64 = false; 351 mask = IO_MASK;352 293 } else { 353 mask = MEM_MASK;354 294 switch ((val >> 1) & 3) { 355 295 case 0: … … 367 307 /* Get the address mask. */ 368 308 pci_conf_write_32(fun, addr, 0xffffffff); 369 mask &= pci_conf_read_32(fun, addr);309 mask = pci_conf_read_32(fun, addr); 370 310 371 311 /* Restore the original value. */ … … 615 555 { 616 556 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops; 617 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;618 557 } 619 558 … … 687 626 size_t pci_bar_mask_to_size(uint32_t mask) 688 627 { 689 size_t size = mask & ~(mask - 1); 690 return size; 628 return ((mask & 0xfffffff0) ^ 0xffffffff) + 1; 691 629 } 692 630
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