Changeset aecf79f in mainline for kernel/arch/xen32/include


Ignore:
Timestamp:
2006-07-24T16:07:15Z (19 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c59dd1a2
Parents:
7b0599b
Message:

xen memory initialization

Location:
kernel/arch/xen32/include
Files:
1 added
3 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/xen32/include/asm.h

    • Property mode changed from 120000 to 100644
    r7b0599b raecf79f  
    1 ../../ia32/include/asm.h
     1/*
     2 * Copyright (C) 2001-2004 Jakub Jermar
     3 * Copyright (C) 2005 Sergey Bondari
     4 * All rights reserved.
     5 *
     6 * Redistribution and use in source and binary forms, with or without
     7 * modification, are permitted provided that the following conditions
     8 * are met:
     9 *
     10 * - Redistributions of source code must retain the above copyright
     11 *   notice, this list of conditions and the following disclaimer.
     12 * - Redistributions in binary form must reproduce the above copyright
     13 *   notice, this list of conditions and the following disclaimer in the
     14 *   documentation and/or other materials provided with the distribution.
     15 * - The name of the author may not be used to endorse or promote products
     16 *   derived from this software without specific prior written permission.
     17 *
     18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28 */
     29
     30/** @addtogroup xen32
     31 * @{
     32 */
     33/** @file
     34 */
     35
     36#ifndef __xen32_ASM_H__
     37#define __xen32_ASM_H__
     38
     39#include <arch/pm.h>
     40#include <arch/types.h>
     41#include <config.h>
     42
     43extern uint32_t interrupt_handler_size;
     44
     45extern void paging_on(void);
     46
     47extern void interrupt_handlers(void);
     48
     49extern void enable_l_apic_in_msr(void);
     50
     51
     52extern void asm_delay_loop(uint32_t t);
     53extern void asm_fake_loop(uint32_t t);
     54
     55
     56/** Halt CPU
     57 *
     58 * Halt the current CPU until interrupt event.
     59 */
     60static inline void cpu_halt(void) { __asm__("hlt\n"); };
     61static inline void cpu_sleep(void) { __asm__("hlt\n"); };
     62
     63#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     64    { \
     65        unative_t res; \
     66        __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
     67        return res; \
     68    }
     69
     70#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     71    { \
     72        __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
     73    }
     74
     75GEN_READ_REG(cr0);
     76GEN_READ_REG(cr2);
     77GEN_READ_REG(cr3);
     78GEN_WRITE_REG(cr3);
     79
     80GEN_READ_REG(dr0);
     81GEN_READ_REG(dr1);
     82GEN_READ_REG(dr2);
     83GEN_READ_REG(dr3);
     84GEN_READ_REG(dr6);
     85GEN_READ_REG(dr7);
     86
     87GEN_WRITE_REG(dr0);
     88GEN_WRITE_REG(dr1);
     89GEN_WRITE_REG(dr2);
     90GEN_WRITE_REG(dr3);
     91GEN_WRITE_REG(dr6);
     92GEN_WRITE_REG(dr7);
     93
     94/** Byte to port
     95 *
     96 * Output byte to port
     97 *
     98 * @param port Port to write to
     99 * @param val Value to write
     100 */
     101static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
     102
     103/** Word to port
     104 *
     105 * Output word to port
     106 *
     107 * @param port Port to write to
     108 * @param val Value to write
     109 */
     110static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
     111
     112/** Double word to port
     113 *
     114 * Output double word to port
     115 *
     116 * @param port Port to write to
     117 * @param val Value to write
     118 */
     119static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
     120
     121/** Byte from port
     122 *
     123 * Get byte from port
     124 *
     125 * @param port Port to read from
     126 * @return Value read
     127 */
     128static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
     129
     130/** Word from port
     131 *
     132 * Get word from port
     133 *
     134 * @param port Port to read from
     135 * @return Value read
     136 */
     137static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
     138
     139/** Double word from port
     140 *
     141 * Get double word from port
     142 *
     143 * @param port Port to read from
     144 * @return Value read
     145 */
     146static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
     147
     148/** Enable interrupts.
     149 *
     150 * Enable interrupts and return previous
     151 * value of EFLAGS.
     152 *
     153 * @return Old interrupt priority level.
     154 */
     155static inline ipl_t interrupts_enable(void)
     156{
     157        ipl_t v;
     158        __asm__ volatile (
     159                "pushf\n\t"
     160                "popl %0\n\t"
     161                "sti\n"
     162                : "=r" (v)
     163        );
     164        return v;
     165}
     166
     167/** Disable interrupts.
     168 *
     169 * Disable interrupts and return previous
     170 * value of EFLAGS.
     171 *
     172 * @return Old interrupt priority level.
     173 */
     174static inline ipl_t interrupts_disable(void)
     175{
     176        ipl_t v;
     177        __asm__ volatile (
     178                "pushf\n\t"
     179                "popl %0\n\t"
     180                "cli\n"
     181                : "=r" (v)
     182        );
     183        return v;
     184}
     185
     186/** Restore interrupt priority level.
     187 *
     188 * Restore EFLAGS.
     189 *
     190 * @param ipl Saved interrupt priority level.
     191 */
     192static inline void interrupts_restore(ipl_t ipl)
     193{
     194        __asm__ volatile (
     195                "pushl %0\n\t"
     196                "popf\n"
     197                : : "r" (ipl)
     198        );
     199}
     200
     201/** Return interrupt priority level.
     202 *
     203 * @return EFLAFS.
     204 */
     205static inline ipl_t interrupts_read(void)
     206{
     207        ipl_t v;
     208        __asm__ volatile (
     209                "pushf\n\t"
     210                "popl %0\n"
     211                : "=r" (v)
     212        );
     213        return v;
     214}
     215
     216/** Return base address of current stack
     217 *
     218 * Return the base address of the current stack.
     219 * The stack is assumed to be STACK_SIZE bytes long.
     220 * The stack must start on page boundary.
     221 */
     222static inline uintptr_t get_stack_base(void)
     223{
     224        uintptr_t v;
     225       
     226        __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
     227       
     228        return v;
     229}
     230
     231static inline uint64_t rdtsc(void)
     232{
     233        uint64_t v;
     234       
     235        __asm__ volatile("rdtsc\n" : "=A" (v));
     236       
     237        return v;
     238}
     239
     240/** Return current IP address */
     241static inline uintptr_t * get_ip()
     242{
     243        uintptr_t *ip;
     244
     245        __asm__ volatile (
     246                "mov %%eip, %0"
     247                : "=r" (ip)
     248                );
     249        return ip;
     250}
     251
     252/** Invalidate TLB Entry.
     253 *
     254 * @param addr Address on a page whose TLB entry is to be invalidated.
     255 */
     256static inline void invlpg(uintptr_t addr)
     257{
     258        __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
     259}
     260
     261/** Load GDTR register from memory.
     262 *
     263 * @param gdtr_reg Address of memory from where to load GDTR.
     264 */
     265static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
     266{
     267        __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
     268}
     269
     270/** Store GDTR register to memory.
     271 *
     272 * @param gdtr_reg Address of memory to where to load GDTR.
     273 */
     274static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
     275{
     276        __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
     277}
     278
     279/** Load IDTR register from memory.
     280 *
     281 * @param idtr_reg Address of memory from where to load IDTR.
     282 */
     283static inline void idtr_load(ptr_16_32_t *idtr_reg)
     284{
     285        __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
     286}
     287
     288/** Load TR from descriptor table.
     289 *
     290 * @param sel Selector specifying descriptor of TSS segment.
     291 */
     292static inline void tr_load(uint16_t sel)
     293{
     294        __asm__ volatile ("ltr %0" : : "r" (sel));
     295}
     296
     297#endif
     298
     299/** @}
     300 */

  • kernel/arch/xen32/include/hypercall.h

    r7b0599b raecf79f  
    3131
    3232#include <arch/types.h>
     33#include <macros.h>
     34
     35
     36#define XEN_CONSOLE_IO  18
     37
     38
     39/*
     40 * Commands for XEN_CONSOLE_IO
     41 */
     42#define CONSOLE_IO_WRITE        0
     43#define CONSOLE_IO_READ         1
     44
    3345
    3446#define hypercall0(id)  \
    … …  
    8395                        : "1" (p1),     \
    8496                          "2" (p2),     \
    85                           "3" (p3),     \
     97                          "3" (p3)      \
    8698                        : "memory"      \
    8799                );      \
    … …  
    102114                          "2" (p2),     \
    103115                          "3" (p3),     \
    104                           "4" (p4),     \
     116                          "4" (p4)      \
    105117                        : "memory"      \
    106118                );      \
    … …  
    110122#define hypercall5(id, p1, p2, p3, p4, p5)      \
    111123        ({      \
    112                 unative_t ret, __ign1, __ign2, __ign3, __ign4, __ing5;  \
     124                unative_t ret, __ign1, __ign2, __ign3, __ign4, __ign5;  \
    113125                asm volatile (  \
    114126                        "call hypercall_page + (" STRING(id) " * 32)\n" \
    … …  
    123135                          "3" (p3),     \
    124136                          "4" (p4),     \
    125                           "5" (p5),     \
     137                          "5" (p5)      \
    126138                        : "memory"      \
    127139                );      \
    … …  
    130142
    131143
    132 static inline int xen_console_io(int cmd, int count, char *str)
     144static inline int xen_console_io(const int cmd, const int count, const char *str)
    133145{
    134146        return hypercall3(XEN_CONSOLE_IO, cmd, count, str);

  • kernel/arch/xen32/include/pm.h

    • Property mode changed from 120000 to 100644
    r7b0599b raecf79f  
    1 ../../ia32/include/pm.h
     1/*
     2 * Copyright (C) 2001-2004 Jakub Jermar
     3 * All rights reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions
     7 * are met:
     8 *
     9 * - Redistributions of source code must retain the above copyright
     10 *   notice, this list of conditions and the following disclaimer.
     11 * - Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 * - The name of the author may not be used to endorse or promote products
     15 *   derived from this software without specific prior written permission.
     16 *
     17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27 */
     28
     29/** @addtogroup xen32
     30 * @{
     31 */
     32/** @file
     33 */
     34
     35#ifndef __PM_H__
     36#define __PM_H__
     37
     38#define IDT_ITEMS 64
     39#define GDT_ITEMS 7
     40
     41#define NULL_DES        0
     42#define KTEXT_DES       1
     43#define KDATA_DES       2
     44#define UTEXT_DES       3
     45#define UDATA_DES       4
     46#define TSS_DES         5
     47#define TLS_DES         6 /* Pointer to Thread-Local-Storage data */
     48
     49#define selector(des)   ((des) << 3)
     50
     51#define PL_KERNEL       1
     52#define PL_USER         3
     53
     54#define AR_PRESENT      (1<<7)
     55#define AR_DATA         (2<<3)
     56#define AR_CODE         (3<<3)
     57#define AR_WRITABLE     (1<<1)
     58#define AR_INTERRUPT    (0xe)
     59#define AR_TSS          (0x9)
     60
     61#define DPL_KERNEL      (PL_KERNEL<<5)
     62#define DPL_USER        (PL_USER<<5)
     63
     64#define TSS_BASIC_SIZE  104
     65#define TSS_IOMAP_SIZE  (16*1024+1)     /* 16K for bitmap + 1 terminating byte for convenience */
     66
     67#define IO_PORTS        (64*1024)
     68
     69#ifndef __ASM__
     70
     71#include <arch/types.h>
     72#include <typedefs.h>
     73#include <arch/context.h>
     74
     75struct ptr_16_32 {
     76        uint16_t limit;
     77        uint32_t base;
     78} __attribute__ ((packed));
     79typedef struct ptr_16_32 ptr_16_32_t;
     80
     81struct descriptor {
     82        unsigned limit_0_15: 16;
     83        unsigned base_0_15: 16;
     84        unsigned base_16_23: 8;
     85        unsigned access: 8;
     86        unsigned limit_16_19: 4;
     87        unsigned available: 1;
     88        unsigned unused: 1;
     89        unsigned special: 1;
     90        unsigned granularity : 1;
     91        unsigned base_24_31: 8;
     92} __attribute__ ((packed));
     93typedef struct descriptor  descriptor_t;
     94
     95struct idescriptor {
     96        unsigned offset_0_15: 16;
     97        unsigned selector: 16;
     98        unsigned unused: 8;
     99        unsigned access: 8;
     100        unsigned offset_16_31: 16;
     101} __attribute__ ((packed));
     102typedef struct idescriptor idescriptor_t;
     103
     104struct tss {
     105        uint16_t link;
     106        unsigned : 16;
     107        uint32_t esp0;
     108        uint16_t ss0;
     109        unsigned : 16;
     110        uint32_t esp1;
     111        uint16_t ss1;
     112        unsigned : 16;
     113        uint32_t esp2;
     114        uint16_t ss2;
     115        unsigned : 16;
     116        uint32_t cr3;
     117        uint32_t eip;
     118        uint32_t eflags;
     119        uint32_t eax;
     120        uint32_t ecx;
     121        uint32_t edx;
     122        uint32_t ebx;
     123        uint32_t esp;
     124        uint32_t ebp;
     125        uint32_t esi;
     126        uint32_t edi;
     127        uint16_t es;
     128        unsigned : 16;
     129        uint16_t cs;
     130        unsigned : 16;
     131        uint16_t ss;
     132        unsigned : 16;
     133        uint16_t ds;
     134        unsigned : 16;
     135        uint16_t fs;
     136        unsigned : 16;
     137        uint16_t gs;
     138        unsigned : 16;
     139        uint16_t ldtr;
     140        unsigned : 16;
     141        unsigned : 16;
     142        uint16_t iomap_base;
     143        uint8_t iomap[TSS_IOMAP_SIZE];
     144} __attribute__ ((packed));
     145typedef struct tss tss_t;
     146
     147extern ptr_16_32_t gdtr;
     148extern ptr_16_32_t bootstrap_gdtr;
     149extern ptr_16_32_t protected_ap_gdtr;
     150extern struct tss *tss_p;
     151
     152extern descriptor_t gdt[];
     153
     154extern void pm_init(void);
     155
     156extern void gdt_setbase(descriptor_t *d, uintptr_t base);
     157extern void gdt_setlimit(descriptor_t *d, uint32_t limit);
     158
     159extern void idt_init(void);
     160extern void idt_setoffset(idescriptor_t *d, uintptr_t offset);
     161
     162extern void tss_initialize(tss_t *t);
     163extern void set_tls_desc(uintptr_t tls);
     164
     165#endif /* __ASM__ */
     166
     167#endif
     168
     169/** @}
     170 */
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