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-              rb277bef
+              rae7d03c
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
          /* ICache coherency is elaborated on in barrier.h.
           * VIPT and PIPT caches need maintenance only on code modify,
           * so it should be safe for general use.
           * Enable branch predictors too as they follow the same rules
           * as ICache and they can be flushed together
           */
+        /* ICache coherency is elaborated on in barrier.h.
+         * VIPT and PIPT caches need maintenance only on code modify,
+         * so it should be safe for general use.
+         * Enable branch predictors too as they follow the same rules
+         * as ICache and they can be flushed together
+         */
         if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
                 control_reg |=

kernel/arch/arm32/src/exception.c

rb277bef	rae7d03c
68	68	/* relative address (related to exc. vector) of the word
69	69	* where handler's address is stored
70		*/
	70	*/
71	71	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
72	72	PREFETCH_OFFSET;

-              rb277bef
+              rae7d03c
         amdm37x_gpt_irq_ack(&beagleboard.timer);
         /*
          * We are holding a lock which prevents preemption.
          * Release the lock, call clock() and reacquire the lock again.
          */
+        /*
+         * We are holding a lock which prevents preemption.
+         * Release the lock, call clock() and reacquire the lock again.
+         */
         spinlock_unlock(&irq->lock);
         clock();

-              rb277bef
+              rae7d03c
+{
         /*
         * We are holding a lock which prevents preemption.
         * Release the lock, call clock() and reacquire the lock again.
         */
+         * We are holding a lock which prevents preemption.
+         * Release the lock, call clock() and reacquire the lock again.
+         */
         spinlock_unlock(&irq->lock);

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