Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 590ce3527c7e162ec44505a60af15990b12de366)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision ae36ba018b1d7b25373160d519fbd7904dcba09c)
@@ -38,4 +38,5 @@
 #include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
 #include <genarch/drivers/amdm37x_gpt/amdm37x_gpt.h>
+#include <genarch/srln/srln.h>
 #include <interrupt.h>
 #include <mm/km.h>
@@ -55,5 +56,5 @@
 
 #define BBXM_MEMORY_START	0x80000000	/* physical */
-#define BBXM_MEMORY_SIZE	0x10000000	/* 256 MB, first chunk */
+#define BBXM_MEMORY_SIZE	0x20000000	/* 512 MB */
 
 static struct beagleboard {
@@ -87,7 +88,7 @@
          * Release the lock, call clock() and reacquire the lock again.
          */
-        spinlock_unlock(&irq->lock);
-        clock();
-        spinlock_lock(&irq->lock);
+	spinlock_unlock(&irq->lock);
+	clock();
+	spinlock_lock(&irq->lock);
 }
 
@@ -100,10 +101,13 @@
 	amdm37x_irc_init(beagleboard.irc_addr);
 
-	// TODO: setup 32kHz clock source for timer1
-
-	/* Initialize timer, pick timer1, beacues it is in always power domain
+	// TODO find a nicer way to setup 32kHz clock source for timer1
+	ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
+	*clksel &= ~1;
+	km_unmap((uintptr_t)clksel, 4);
+
+	/* Initialize timer, pick timer1, because it is in always-power domain
 	 * and has special capabilities for regular ticks */
 	amdm37x_gpt_timer_ticks_init(&beagleboard.timer,
-	    AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, 100);
+	    AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, 100); /* 100 Hz */
 }
 
@@ -175,4 +179,10 @@
 static void bbxm_input_init(void)
 {
+	srln_instance_t *srln_instance = srln_init();
+	if (srln_instance) {
+		indev_t *sink = stdin_wire();
+		indev_t *srln = srln_wire(srln_instance, sink);
+		amdm37x_uart_input_wire(&beagleboard.uart, srln);
+	}
 }
 
