Changeset add04f7 in mainline for kernel/arch/ia32/src

Timestamp:

2009-03-03T15:20:49Z (16 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f24d300

Parents:

deca67b

Message:

better inline assembler readability using the new symbolic syntax

Location:

kernel/arch/ia32/src

Files:

• cpu/cpu.c (modified) (5 diffs)
• fpu_context.c (modified) (6 diffs)
• interrupt.c (modified) (1 diff)
• pm.c (modified) (3 diffs)
• userspace.c (modified) (3 diffs)

kernel/arch/ia32/src/cpu/cpu.c

@@ -49 +49 @@
  * Contains only non-MP-Specification specific SMP code.
  */
-#define AMD_CPUID_EBX   0x68747541
-#define AMD_CPUID_ECX   0x444d4163
-#define AMD_CPUID_EDX   0x69746e65
+#define AMD_CPUID_EBX  0x68747541
+#define AMD_CPUID_ECX  0x444d4163
+#define AMD_CPUID_EDX  0x69746e65
 
-#define INTEL_CPUID_EBX 0x756e6547
-#define INTEL_CPUID_ECX 0x6c65746e
-#define INTEL_CPUID_EDX 0x49656e69
+#define INTEL_CPUID_EBX  0x756e6547
+#define INTEL_CPUID_ECX  0x6c65746e
+#define INTEL_CPUID_EDX  0x49656e69
 
 
 enum vendor {
-        VendorUnknown=0,
+        VendorUnknown = 0,
         VendorAMD,
         VendorIntel
@@ -73 +73 @@
 {
         asm volatile (
-                "mov %%cr0,%%eax;"
-                "or $8,%%eax;"
-                "mov %%eax,%%cr0;"
-                :
-                :
-                : "%eax"
+                "mov %%cr0, %%eax\n"
+                "or $8, %%eax\n"
+                "mov %%eax, %%cr0\n"
+                ::: "%eax"
         );
 }
@@ -85 +83 @@
 {
         asm volatile (
-                "mov %%cr0,%%eax;"
-                "and $0xffFFffF7,%%eax;"
-                "mov %%eax,%%cr0;"
-                :
-                :
-                : "%eax"
-        );      
+                "mov %%cr0, %%eax\n"
+                "and $0xffFFffF7, %%eax\n"
+                "mov %%eax,%%cr0\n"
+                ::: "%eax"
+        );
 }
 
@@ -103 +99 @@
         CPU->arch.tss = tss_p;
         CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
-
+        
         CPU->fpu_owner = NULL;
-
+        
         cpuid(1, &info);
-
+        
         fi.word = info.cpuid_edx;
         efi.word = info.cpuid_ecx;
@@ -114 +110 @@
                 fpu_fxsr();
         else
-                fpu_fsr();      
+                fpu_fsr();
         
         if (fi.bits.sse) {
                 asm volatile (
-                        "mov %%cr4,%0\n"
-                        "or %1,%0\n"
-                        "mov %0,%%cr4\n"
-                        : "+r" (help)
-                        : "i" (CR4_OSFXSR_MASK|(1<<10)) 
+                        "mov %%cr4, %[help]\n"
+                        "or %[mask], %[help]\n"
+                        "mov %[help], %%cr4\n"
+                        : [help] "+r" (help)
+                        : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
                 );
         }

kernel/arch/ia32/src/fpu_context.c

@@ -45 +45 @@
 {
         asm volatile (
-                "fnsave %0"
-                : "=m"(*fctx)
-                );
+                "fnsave %[fctx]"
+                : [fctx] "=m" (*fctx)
+        );
 }
 
@@ -53 +53 @@
 {
         asm volatile (
-                "frstor %0"
-                : "=m"(*fctx)
-                );
+                "frstor %[fctx]"
+                : [fctx] "=m" (*fctx)
+        );
 }
 
@@ -61 +61 @@
 {
         asm volatile (
-                "fxsave %0"
-                : "=m"(*fctx)
-                );
+                "fxsave %[fctx]"
+                : [fctx] "=m" (*fctx)
+        );
 }
 
@@ -69 +69 @@
 {
         asm volatile (
-                "fxrstor %0"
-                : "=m"(*fctx)
-                );
+                "fxrstor %[fctx]"
+                : [fctx] "=m" (*fctx)
+        );
 }
 
-/*
-        Setup using fxsr instruction
-*/
+/* Setup using fxsr instruction */
 void fpu_fxsr(void)
 {
@@ -82 +80 @@
         fpu_restore=fpu_context_fx_restore;
 }
-/*
-        Setup using not fxsr instruction
-*/
+
+/* Setup using not fxsr instruction */
 void fpu_fsr(void)
 {
@@ -103 +100 @@
 void fpu_init()
 {
-        uint32_t help0 = 0, help1 = 0;
+        uint32_t help0 = 0;
+        uint32_t help1 = 0;
+        
         asm volatile (
-                "fninit;\n"
-                "stmxcsr %0\n"
-                "mov %0,%1;\n"
-                "or %2,%1;\n"
-                "mov %1,%0;\n"
-                "ldmxcsr %0;\n"
-                : "+m" (help0), "+r" (help1)
-                : "i" (0x1f80)
+                "fninit\n"
+                "stmxcsr %[help0]\n"
+                "mov %[help0], %[help1]\n"
+                "or %[magic], %[help1]\n"
+                "mov %[help1], %[help0]\n"
+                "ldmxcsr %[help0]\n"
+                : [help0] "+m" (help0), [help1] "+r" (help1)
+                : [magic] "i" (0x1f80)
         );
 }

kernel/arch/ia32/src/interrupt.c

@@ -139 +139 @@
         uint32_t mxcsr;
         asm (
-                "stmxcsr %0;\n"
-                : "=m" (mxcsr)
+                "stmxcsr %[mxcsr]\n"
+                : [mxcsr] "=m" (mxcsr)
         );
         fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx.",
             (unative_t) mxcsr);
-
+        
         decode_istate(istate);
         printf("MXCSR: %#lx\n", mxcsr);

kernel/arch/ia32/src/pm.c

@@ -27 +27 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -155 +155 @@
                 "push %%eax\n"
                 "popfl\n"
-                : : : "eax"
+                ::: "eax"
         );
 }
@@ -166 +166 @@
                 "and $0xfffbffff, %%eax\n"
                 "mov %%eax, %%cr0\n"
-                : : : "eax"
+                ::: "eax"
         );
 }

kernel/arch/ia32/src/userspace.c

@@ -27 +27 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -48 +48 @@
 void userspace(uspace_arg_t *kernel_uarg)
 {
-        ipl_t ipl;
-
-        ipl = interrupts_disable();
-
+        ipl_t ipl = interrupts_disable();
+        
         asm volatile (
                 /*
@@ -61 +59 @@
                 "push %%eax\n"
                 "popfl\n"
-
+                
                 /* Set up GS register (TLS) */
-                "movl %6, %%gs\n"
-
-                "pushl %0\n"
-                "pushl %1\n"
-                "pushl %2\n"
-                "pushl %3\n"
-                "pushl %4\n"
-                "movl %5, %%eax\n"
-
+                "movl %[tls_des], %%gs\n"
+                
+                "pushl %[udata_des]\n"
+                "pushl %[stack_size]\n"
+                "pushl %[ipl]\n"
+                "pushl %[utext_des]\n"
+                "pushl %[entry]\n"
+                "movl %[uarg], %%eax\n"
+                
                 /* %ebx is defined to hold pcb_ptr - set it to 0 */
-                "xorl %%ebx, %%ebx\n"   
-
+                "xorl %%ebx, %%ebx\n"
+                
                 "iret\n"
-                : 
-                : "i" (selector(UDATA_DES) | PL_USER),
-                  "r" ((uint8_t *) kernel_uarg->uspace_stack +
-                      THREAD_STACK_SIZE),
-                  "r" (ipl),
-                  "i" (selector(UTEXT_DES) | PL_USER),
-                  "r" (kernel_uarg->uspace_entry),
-                  "r" (kernel_uarg->uspace_uarg),
-                  "r" (selector(TLS_DES))
+                :
+                : [udata_des] "i" (selector(UDATA_DES) | PL_USER),
+                  [stack_size] "r" ((uint8_t *) kernel_uarg->uspace_stack + THREAD_STACK_SIZE),
+                  [ipl] "r" (ipl),
+                  [utext_des] "i" (selector(UTEXT_DES) | PL_USER),
+                  [entry] "r" (kernel_uarg->uspace_entry),
+                  [uarg] "r" (kernel_uarg->uspace_uarg),
+                  [tls_des] "r" (selector(TLS_DES))
                 : "eax");
         
         /* Unreachable */
-        for(;;)
-                ;
+        while (1);
 }