Changes in kernel/arch/ia32/src/interrupt.c [98000fb:acc7ce4] in mainline
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kernel/arch/ia32/src/interrupt.c
r98000fb racc7ce4 53 53 #include <ddi/irq.h> 54 54 #include <symtab.h> 55 #include <stacktrace.h> 55 56 56 57 /* … … 61 62 void (* enable_irqs_function)(uint16_t irqmask) = NULL; 62 63 void (* eoi_function)(void) = NULL; 63 64 void decode_istate(istate_t *istate) 65 { 66 char *symbol; 67 68 symbol = symtab_fmt_name_lookup(istate->eip); 69 70 if (CPU) 71 printf("----------------EXCEPTION OCCURED (cpu%u)----------------\n", CPU->id); 72 else 73 printf("----------------EXCEPTION OCCURED----------------\n"); 74 75 printf("%%eip: %#lx (%s)\n", istate->eip, symbol); 76 printf("ERROR_WORD=%#lx\n", istate->error_word); 77 printf("%%cs=%#lx,flags=%#lx\n", istate->cs, istate->eflags); 78 printf("%%eax=%#lx, %%ecx=%#lx, %%edx=%#lx, %%esp=%p\n", istate->eax, istate->ecx, istate->edx, &istate->stack[0]); 79 printf("stack: %#lx, %#lx, %#lx, %#lx\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); 80 printf(" %#lx, %#lx, %#lx, %#lx\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); 64 const char *irqs_info = NULL; 65 66 void istate_decode(istate_t *istate) 67 { 68 printf("cs =%#0" PRIx32 "\teip=%p\t" 69 "efl=%#0" PRIx32 "\terr=%#0" PRIx32 "\n", 70 istate->cs, (void *) istate->eip, 71 istate->eflags, istate->error_word); 72 73 printf("ds =%#0" PRIx32 "\tes =%#0" PRIx32 "\t" 74 "fs =%#0" PRIx32 "\tgs =%#0" PRIx32 "\n", 75 istate->ds, istate->es, istate->fs, istate->gs); 76 77 if (istate_from_uspace(istate)) 78 printf("ss =%#0" PRIx32 "\n", istate->ss); 79 80 printf("eax=%#0" PRIx32 "\tebx=%#0" PRIx32 "\t" 81 "ecx=%#0" PRIx32 "\tedx=%#0" PRIx32 "\n", 82 istate->eax, istate->ebx, istate->ecx, istate->edx); 83 84 printf("esi=%p\tedi=%p\tebp=%p\tesp=%p\n", 85 (void *) istate->esi, (void *) istate->edi, 86 (void *) istate->ebp, 87 istate_from_uspace(istate) ? ((void *) istate->esp) : 88 &istate->esp); 81 89 } 82 90 … … 90 98 } 91 99 92 static void null_interrupt(int n, istate_t *istate) 93 { 94 fault_if_from_uspace(istate, "Unserviced interrupt: %d.", n); 95 96 decode_istate(istate); 97 panic("Unserviced interrupt: %d.", n); 100 static void null_interrupt(unsigned int n, istate_t *istate) 101 { 102 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n); 103 panic_badtrap(istate, n, "Unserviced interrupt: %u.", n); 104 } 105 106 static void de_fault(unsigned int n, istate_t *istate) 107 { 108 fault_if_from_uspace(istate, "Divide error."); 109 panic_badtrap(istate, n, "Divide error."); 98 110 } 99 111 100 112 /** General Protection Fault. */ 101 static void gp_fault( int n __attribute__((unused)), istate_t *istate)113 static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate) 102 114 { 103 115 if (TASK) { 104 size_t ver; 116 irq_spinlock_lock(&TASK->lock, false); 117 size_t ver = TASK->arch.iomapver; 118 irq_spinlock_unlock(&TASK->lock, false); 105 119 106 spinlock_lock(&TASK->lock);107 ver = TASK->arch.iomapver;108 spinlock_unlock(&TASK->lock);109 110 120 if (CPU->arch.iomapver_copy != ver) { 111 121 /* … … 121 131 fault_if_from_uspace(istate, "General protection fault."); 122 132 } 123 124 decode_istate(istate); 125 panic("General protection fault."); 126 } 127 128 static void ss_fault(int n __attribute__((unused)), istate_t *istate) 133 panic_badtrap(istate, n, "General protection fault."); 134 } 135 136 static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate) 129 137 { 130 138 fault_if_from_uspace(istate, "Stack fault."); 131 132 decode_istate(istate); 133 panic("Stack fault."); 134 } 135 136 static void simd_fp_exception(int n __attribute__((unused)), istate_t *istate) 139 panic_badtrap(istate, n, "Stack fault."); 140 } 141 142 static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate) 137 143 { 138 144 uint32_t mxcsr; 139 asm (145 asm volatile ( 140 146 "stmxcsr %[mxcsr]\n" 141 147 : [mxcsr] "=m" (mxcsr) 142 148 ); 143 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx.", 144 (unative_t) mxcsr); 145 146 decode_istate(istate); 147 printf("MXCSR: %#lx\n", mxcsr); 148 panic("SIMD FP exception(19)."); 149 } 150 151 static void nm_fault(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) 152 { 153 #ifdef CONFIG_FPU_LAZY 149 150 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".", 151 mxcsr); 152 panic_badtrap(istate, n, "SIMD FP exception"); 153 } 154 155 static void nm_fault(unsigned int n __attribute__((unused)), 156 istate_t *istate __attribute__((unused))) 157 { 158 #ifdef CONFIG_FPU_LAZY 154 159 scheduler_fpu_lazy_request(); 155 160 #else 156 161 fault_if_from_uspace(istate, "FPU fault."); 157 panic ("FPU fault.");162 panic_badtrap(istate, n, "FPU fault."); 158 163 #endif 159 164 } 160 165 161 166 #ifdef CONFIG_SMP 162 static void tlb_shootdown_ipi(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) 167 static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)), 168 istate_t *istate __attribute__((unused))) 163 169 { 164 170 trap_virtual_eoi(); … … 168 174 169 175 /** Handler of IRQ exceptions */ 170 static void irq_interrupt( int n, istate_t *istate __attribute__((unused)))176 static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused))) 171 177 { 172 178 ASSERT(n >= IVT_IRQBASE); 173 179 174 int inum = n - IVT_IRQBASE;180 unsigned int inum = n - IVT_IRQBASE; 175 181 bool ack = false; 176 182 ASSERT(inum < IRQ_COUNT); … … 182 188 * The IRQ handler was found. 183 189 */ 184 190 185 191 if (irq->preack) { 186 192 /* Send EOI before processing the interrupt */ … … 189 195 } 190 196 irq->handler(irq); 191 spinlock_unlock(&irq->lock);197 irq_spinlock_unlock(&irq->lock, false); 192 198 } else { 193 199 /* … … 195 201 */ 196 202 #ifdef CONFIG_DEBUG 197 printf("cpu%u: spurious interrupt (inum=% d)\n", CPU->id, inum);203 printf("cpu%u: spurious interrupt (inum=%u)\n", CPU->id, inum); 198 204 #endif 199 205 } … … 205 211 void interrupt_init(void) 206 212 { 207 int i;213 unsigned int i; 208 214 209 215 for (i = 0; i < IVT_ITEMS; i++) 210 exc_register(i, "null", (iroutine) null_interrupt);216 exc_register(i, "null", false, (iroutine_t) null_interrupt); 211 217 212 218 for (i = 0; i < IRQ_COUNT; i++) { 213 219 if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) 214 exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); 220 exc_register(IVT_IRQBASE + i, "irq", true, 221 (iroutine_t) irq_interrupt); 215 222 } 216 223 217 exc_register(7, "nm_fault", (iroutine) nm_fault); 218 exc_register(12, "ss_fault", (iroutine) ss_fault); 219 exc_register(13, "gp_fault", (iroutine) gp_fault); 220 exc_register(19, "simd_fp", (iroutine) simd_fp_exception); 224 exc_register(0, "de_fault", true, (iroutine_t) de_fault); 225 exc_register(7, "nm_fault", true, (iroutine_t) nm_fault); 226 exc_register(12, "ss_fault", true, (iroutine_t) ss_fault); 227 exc_register(13, "gp_fault", true, (iroutine_t) gp_fault); 228 exc_register(19, "simd_fp", true, (iroutine_t) simd_fp_exception); 221 229 222 230 #ifdef CONFIG_SMP 223 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); 231 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true, 232 (iroutine_t) tlb_shootdown_ipi); 224 233 #endif 225 234 }
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