Changeset a82500ce in mainline for arch/ia64/src

Timestamp:

2006-03-12T17:32:01Z (20 years ago)

Author:

Jakub Vana <jakub.vana@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

de6b301

Parents:

12f952e5

Message:

Two frame stack (standard stack + RSE) on Itanium

Location:

arch/ia64/src

Files:

• mm/tlb.c (modified) (1 diff)
• proc/scheduler.c (modified) (1 diff)

arch/ia64/src/mm/tlb.c

@@ -89 +89 @@
 {
         /* TODO */
-}
+        tlb_invalidate_all();
+}
+
+
+void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
+{
+
+
+}
+
 
 /** Insert data into data translation cache.

arch/ia64/src/proc/scheduler.c

@@ -63 +63 @@
                 "bsw.1\n"
                 :
-                : "r" (((__address) THREAD->kstack) + ALIGN_UP(sizeof(the_t), REGISTER_STACK_ALIGNMENT)),
-                  "r" (&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]));
+                : /*"r" (((__address) THREAD->kstack) + ALIGN_UP(sizeof(the_t), REGISTER_STACK_ALIGNMENT)),*/
+                  "r" (&THREAD->kstack[THREAD_STACK_SIZE]),
+                  "r" (&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA])
+                );
 }