Changeset a35b458 in mainline for uspace/lib/c/arch
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- Location:
- uspace/lib/c/arch
- Files:
-
- 43 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/lib/c/arch/abs32le/include/libarch/atomic.h
r3061bc1 ra35b458 49 49 return true; 50 50 } 51 51 52 52 return false; 53 53 } … … 57 57 /* On real hardware the increment has to be done 58 58 as an atomic action. */ 59 59 60 60 val->count++; 61 61 } … … 65 65 /* On real hardware the decrement has to be done 66 66 as an atomic action. */ 67 67 68 68 val->count++; 69 69 } … … 74 74 value and the increment have to be done as a single 75 75 atomic action. */ 76 76 77 77 atomic_count_t prev = val->count; 78 78 79 79 val->count++; 80 80 return prev; … … 86 86 value and the decrement have to be done as a single 87 87 atomic action. */ 88 88 89 89 atomic_count_t prev = val->count; 90 90 91 91 val->count--; 92 92 return prev; -
uspace/lib/c/arch/amd64/include/libarch/atomic.h
r3061bc1 ra35b458 75 75 { 76 76 atomic_count_t r = 1; 77 77 78 78 #ifdef __PCC__ 79 79 asm volatile ( … … 89 89 ); 90 90 #endif 91 91 92 92 return r; 93 93 } … … 96 96 { 97 97 atomic_count_t r = -1; 98 98 99 99 #ifdef __PCC__ 100 100 asm volatile ( … … 110 110 ); 111 111 #endif 112 112 113 113 return r; 114 114 } -
uspace/lib/c/arch/amd64/src/entry.S
r3061bc1 ra35b458 44 44 pushq $0 45 45 movq %rsp, %rbp 46 46 47 47 # %rdi was deliberately chosen as the first argument is also in %rdi 48 48 # Pass PCB pointer to __main (no operation) -
uspace/lib/c/arch/amd64/src/entryjmp.S
r3061bc1 ra35b458 39 39 push %rbp 40 40 movq %rsp, %rbp 41 41 42 42 # pcb must be passed in %rdi, use %rdx as a scratch register 43 43 mov %rdi, %rdx 44 44 mov %rsi, %rdi 45 45 46 46 # jump to entry point 47 47 jmp *%rdx -
uspace/lib/c/arch/amd64/src/fibril.S
r3061bc1 ra35b458 39 39 FUNCTION_BEGIN(context_save) 40 40 movq (%rsp), %rdx # the caller's return %eip 41 41 42 42 # in %rdi is passed 1st argument 43 43 movq %rdx, CONTEXT_OFFSET_PC(%rdi) 44 44 movq %rsp, CONTEXT_OFFSET_SP(%rdi) 45 45 46 46 movq %rbx, CONTEXT_OFFSET_RBX(%rdi) 47 47 movq %rbp, CONTEXT_OFFSET_RBP(%rdi) … … 50 50 movq %r14, CONTEXT_OFFSET_R14(%rdi) 51 51 movq %r15, CONTEXT_OFFSET_R15(%rdi) 52 52 53 53 movq %fs:0, %rax 54 54 movq %rax, CONTEXT_OFFSET_TLS(%rdi) 55 55 56 56 xorl %eax, %eax # context_save returns 1 57 57 incl %eax … … 71 71 movq CONTEXT_OFFSET_RBP(%rdi), %rbp 72 72 movq CONTEXT_OFFSET_RBX(%rdi), %rbx 73 73 74 74 movq CONTEXT_OFFSET_SP(%rdi), %rsp # ctx->sp -> %rsp 75 75 76 76 movq CONTEXT_OFFSET_PC(%rdi), %rdx 77 77 78 78 movq %rdx,(%rsp) 79 79 80 80 movq CONTEXT_OFFSET_TLS(%rdi), %rdi 81 81 movq %rdi, %fs:0 82 82 83 83 xorl %eax, %eax # context_restore returns 0 84 84 ret -
uspace/lib/c/arch/amd64/src/syscall.S
r3061bc1 ra35b458 30 30 31 31 .text 32 32 33 33 ## Make a system call. 34 34 # -
uspace/lib/c/arch/amd64/src/thread_entry.S
r3061bc1 ra35b458 41 41 pushq $0 42 42 movq %rsp, %rbp 43 43 44 44 # 45 45 # RAX contains address of uarg -
uspace/lib/c/arch/arm32/include/libarch/atomic.h
r3061bc1 ra35b458 49 49 { 50 50 atomic_count_t ret = 0; 51 51 52 52 /* 53 53 * The following instructions between labels 1 and 2 constitute a … … 75 75 : "memory" 76 76 ); 77 77 78 78 ras_page[0] = 0; 79 79 asm volatile ( … … 81 81 ); 82 82 ras_page[1] = 0xffffffff; 83 83 84 84 return ret != 0; 85 85 } … … 96 96 { 97 97 atomic_count_t ret = 0; 98 98 99 99 /* 100 100 * The following instructions between labels 1 and 2 constitute a … … 118 118 : [imm] "r" (i) 119 119 ); 120 120 121 121 ras_page[0] = 0; 122 122 asm volatile ( … … 124 124 ); 125 125 ras_page[1] = 0xffffffff; 126 126 127 127 return ret; 128 128 } -
uspace/lib/c/arch/arm32/src/entry.S
r3061bc1 ra35b458 42 42 ldr r0, =ras_page 43 43 str r2, [r0] 44 44 45 45 # 46 46 # Create the first stack frame. … … 50 50 push {fp, ip, lr, pc} 51 51 sub fp, ip, #4 52 52 53 53 # Pass pcb_ptr to __main as the first argument (in r0) 54 54 mov r0, r1 -
uspace/lib/c/arch/arm32/src/fibril.S
r3061bc1 ra35b458 34 34 stmia r0!, {sp, lr} 35 35 stmia r0!, {r4-r11} 36 36 37 37 # return 1 38 38 mov r0, #1 … … 43 43 ldmia r0!, {sp, lr} 44 44 ldmia r0!, {r4-r11} 45 45 46 46 # return 0 47 47 mov r0, #0 -
uspace/lib/c/arch/arm32/src/syscall.c
r3061bc1 ra35b458 60 60 register sysarg_t __arm_reg_r5 asm("r5") = p6; 61 61 register sysarg_t __arm_reg_r6 asm("r6") = id; 62 62 63 63 asm volatile ( 64 64 "swi 0" … … 72 72 "r" (__arm_reg_r6) 73 73 ); 74 74 75 75 return __arm_reg_r0; 76 76 } -
uspace/lib/c/arch/arm32/src/thread_entry.S
r3061bc1 ra35b458 42 42 push {fp, ip, lr, pc} 43 43 sub fp, ip, #4 44 44 45 45 b __thread_main -
uspace/lib/c/arch/ia32/include/libarch/atomic.h
r3061bc1 ra35b458 73 73 { 74 74 atomic_count_t r = 1; 75 75 76 76 #ifdef __PCC__ 77 77 asm volatile ( … … 87 87 ); 88 88 #endif 89 89 90 90 return r; 91 91 } … … 94 94 { 95 95 atomic_count_t r = -1; 96 96 97 97 #ifdef __PCC__ 98 98 asm volatile ( … … 108 108 ); 109 109 #endif 110 110 111 111 return r; 112 112 } -
uspace/lib/c/arch/ia32/include/libarch/ddi.h
r3061bc1 ra35b458 42 42 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { 43 43 uint8_t val; 44 44 45 45 asm volatile ( 46 46 "inb %w[port], %b[val]\n" … … 48 48 : [port] "d" (port) 49 49 ); 50 50 51 51 return val; 52 52 } else … … 58 58 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { 59 59 uint16_t val; 60 60 61 61 asm volatile ( 62 62 "inw %w[port], %w[val]\n" … … 64 64 : [port] "d" (port) 65 65 ); 66 66 67 67 return val; 68 68 } else … … 74 74 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { 75 75 uint32_t val; 76 76 77 77 asm volatile ( 78 78 "inl %w[port], %[val]\n" … … 80 80 : [port] "d" (port) 81 81 ); 82 82 83 83 return val; 84 84 } else -
uspace/lib/c/arch/ia32/include/libarch/tls.h
r3061bc1 ra35b458 54 54 { 55 55 void *retval; 56 56 57 57 asm volatile ("movl %%gs:0, %0" : "=r" (retval)); 58 58 59 59 return retval; 60 60 } -
uspace/lib/c/arch/ia32/src/entry.S
r3061bc1 ra35b458 46 46 mov %ax, %fs 47 47 # Do not set %gs, it contains descriptor that can see TLS 48 48 49 49 #ifndef PROCESSOR_i486 50 50 # Detect the mechanism used for making syscalls … … 57 57 0: 58 58 #endif 59 59 60 60 # 61 61 # Create the first stack frame. … … 64 64 pushl $0 65 65 movl %esp, %ebp 66 66 67 67 # Pass the PCB pointer to __main as the first argument 68 68 pushl %edi -
uspace/lib/c/arch/ia32/src/entryjmp.S
r3061bc1 ra35b458 36 36 push %ebp 37 37 movl %esp, %ebp 38 38 39 39 # %eax := entry_point 40 40 movl 0x8(%ebp), %eax 41 41 42 42 # %edi := pcb 43 43 # pcb is passed to the entry point in %edi 44 44 mov 0xc(%ebp), %edi 45 45 46 46 # Save a tiny bit of stack space 47 47 pop %ebp 48 48 49 49 jmp *%eax -
uspace/lib/c/arch/ia32/src/fibril.S
r3061bc1 ra35b458 40 40 movl 0(%esp), %eax # the caller's return %eip 41 41 movl 4(%esp), %edx # address of the context variable to save context to 42 42 43 43 # save registers to the context structure 44 44 movl %esp, CONTEXT_OFFSET_SP(%edx) # %esp -> ctx->sp … … 48 48 movl %edi, CONTEXT_OFFSET_EDI(%edx) # %edi -> ctx->edi 49 49 movl %ebp, CONTEXT_OFFSET_EBP(%edx) # %ebp -> ctx->ebp 50 50 51 51 # save TLS 52 52 movl %gs:0, %eax 53 53 movl %eax, CONTEXT_OFFSET_TLS(%edx) # tls -> ctx->tls 54 54 55 55 xorl %eax, %eax # context_save returns 1 56 56 incl %eax … … 65 65 FUNCTION_BEGIN(context_restore) 66 66 movl 4(%esp), %eax # address of the context variable to restore context from 67 67 68 68 # restore registers from the context structure 69 69 movl CONTEXT_OFFSET_SP(%eax),%esp # ctx->sp -> %esp … … 73 73 movl CONTEXT_OFFSET_EDI(%eax),%edi # ctx->edi -> %edi 74 74 movl CONTEXT_OFFSET_EBP(%eax),%ebp # ctx->ebp -> %ebp 75 75 76 76 movl %edx, 0(%esp) # ctx->pc -> saver's return %eip 77 77 78 78 # set thread local storage 79 79 movl CONTEXT_OFFSET_TLS(%eax), %edx # Set arg1 to TLS addr 80 80 movl %edx, %gs:0 81 81 82 82 xorl %eax, %eax # context_restore returns 0 83 83 ret -
uspace/lib/c/arch/ia32/src/rtld/reloc.c
r3061bc1 ra35b458 65 65 elf_word sym_idx; 66 66 uint32_t sym_addr; 67 67 68 68 elf_symbol_t *sym_table; 69 69 elf_symbol_t *sym; … … 71 71 uint32_t sym_size; 72 72 char *str_tab; 73 73 74 74 elf_symbol_t *sym_def; 75 75 module_t *dest; … … 82 82 83 83 DPRINTF("address: 0x%" PRIxPTR ", entries: %zd\n", (uintptr_t)rt, rt_entries); 84 84 85 85 for (i = 0; i < rt_entries; ++i) { 86 86 // DPRINTF("symbol %d: ", i); … … 173 173 memcpy(r_ptr, (const void *)sym_addr, sym_size); 174 174 break; 175 175 176 176 case R_386_RELATIVE: 177 177 DPRINTF("fixup R_386_RELATIVE (b+a)\n"); -
uspace/lib/c/arch/ia32/src/thread_entry.S
r3061bc1 ra35b458 40 40 mov %dx, %fs 41 41 # Do not set %gs, it contains descriptor that can see TLS 42 42 43 43 # 44 44 # Create the first stack frame. … … 47 47 pushl $0 48 48 mov %esp, %ebp 49 49 50 50 # 51 51 # EAX contains address of uarg. … … 53 53 pushl %eax 54 54 call __thread_main 55 55 56 56 # 57 57 # Not reached. -
uspace/lib/c/arch/ia64/include/libarch/atomic.h
r3061bc1 ra35b458 43 43 { 44 44 atomic_count_t v; 45 45 46 46 asm volatile ( 47 47 "fetchadd8.rel %[v] = %[count], 1\n" … … 54 54 { 55 55 atomic_count_t v; 56 56 57 57 asm volatile ( 58 58 "fetchadd8.rel %[v] = %[count], -1\n" … … 65 65 { 66 66 atomic_count_t v; 67 67 68 68 asm volatile ( 69 69 "fetchadd8.rel %[v] = %[count], 1\n" … … 71 71 [count] "+m" (val->count) 72 72 ); 73 73 74 74 return (v + 1); 75 75 } … … 78 78 { 79 79 atomic_count_t v; 80 80 81 81 asm volatile ( 82 82 "fetchadd8.rel %[v] = %[count], -1\n" … … 84 84 [count] "+m" (val->count) 85 85 ); 86 86 87 87 return (v - 1); 88 88 } … … 91 91 { 92 92 atomic_count_t v; 93 93 94 94 asm volatile ( 95 95 "fetchadd8.rel %[v] = %[count], 1\n" … … 97 97 [count] "+m" (val->count) 98 98 ); 99 99 100 100 return v; 101 101 } … … 104 104 { 105 105 atomic_count_t v; 106 106 107 107 asm volatile ( 108 108 "fetchadd8.rel %[v] = %[count], -1\n" … … 110 110 [count] "+m" (val->count) 111 111 ); 112 112 113 113 return v; 114 114 } -
uspace/lib/c/arch/ia64/src/ddi.c
r3061bc1 ra35b458 36 36 if (sysinfo_get_value("ia64_iospace.address.virtual", &addr) != 0) 37 37 addr = 0; 38 38 39 39 return addr; 40 40 } -
uspace/lib/c/arch/ia64/src/entry.S
r3061bc1 ra35b458 40 40 alloc loc0 = ar.pfs, 0, 1, 2, 0 41 41 movl gp = __gp 42 42 43 43 # Pass PCB pointer as the first argument to __main 44 44 mov out0 = r2 ;; -
uspace/lib/c/arch/ia64/src/fibril.S
r3061bc1 ra35b458 45 45 flushrs 46 46 mov loc4 = ar.bsp 47 47 48 48 /* 49 49 * Put RSE to enforced lazy mode. … … 117 117 118 118 mov loc2 = ar.unat 119 119 120 120 /* 121 121 * Save application registers … … 177 177 178 178 mov ar.unat = loc1 179 179 180 180 add r8 = r0, r0, 1 /* context_save returns 1 */ 181 181 br.ret.sptk.many b0 … … 239 239 ld8 loc5 = [loc14] /* load ar.rnat */ 240 240 ld8 loc6 = [loc15] /* load ar.lc */ 241 241 242 242 .auto 243 243 … … 274 274 mov ar.unat = loc2 ;; 275 275 mov ar.lc = loc6 276 276 277 277 /* 278 278 * Restore general registers including NaT bits … … 332 332 ldf.fill f30 = [loc48] 333 333 ldf.fill f31 = [loc49] 334 334 335 335 mov ar.unat = loc1 336 336 337 337 mov r8 = r0 /* context_restore returns 0 */ 338 338 br.ret.sptk.many b0 -
uspace/lib/c/arch/ia64/src/thread_entry.S
r3061bc1 ra35b458 38 38 39 39 movl gp = __gp 40 40 41 41 # 42 42 # r8 contains address of uarg structure. 43 43 # 44 44 45 45 mov out0 = r8 ;; 46 46 br.call.sptk.many b0 = __thread_main 47 47 48 48 # 49 49 # Not reached. -
uspace/lib/c/arch/mips32/include/libarch/atomic.h
r3061bc1 ra35b458 62 62 atomic_count_t tmp; 63 63 atomic_count_t v; 64 64 65 65 asm volatile ( 66 66 "1:\n" … … 77 77 "i" (0) 78 78 ); 79 79 80 80 return v; 81 81 } -
uspace/lib/c/arch/mips32/src/entry.S
r3061bc1 ra35b458 44 44 .frame $sp, ABI_STACK_FRAME, $ra 45 45 .cpload $t9 46 46 47 47 # Allocate the stack frame. 48 48 addiu $sp, -ABI_STACK_FRAME 49 49 50 50 # Allow PIC code 51 51 .cprestore 16 52 52 53 53 # Pass pcb_ptr to __main() as the first argument. It is already 54 54 # in $a0. As the first argument is passed in $a0, no operation 55 55 # is needed. 56 56 57 57 jal __main 58 58 nop 59 59 60 60 # 61 61 # Not reached. -
uspace/lib/c/arch/mips32/src/entryjmp.S
r3061bc1 ra35b458 43 43 # tmp := entry_point 44 44 move $t9, $a0 45 45 46 46 # Pass pcb to the entry point in $a0 47 47 move $a0, $a1 48 48 49 49 jr $t9 50 50 addiu $sp, -ABI_STACK_FRAME -
uspace/lib/c/arch/mips32/src/fibril.S
r3061bc1 ra35b458 46 46 sw $s8, CONTEXT_OFFSET_S8($a0) 47 47 sw $gp, CONTEXT_OFFSET_GP($a0) 48 48 49 49 sw $k1, CONTEXT_OFFSET_TLS($a0) 50 50 51 51 #ifdef CONFIG_FPU 52 52 mfc1 $t0, $20 53 53 sw $t0, CONTEXT_OFFSET_F20($a0) 54 54 55 55 mfc1 $t0, $21 56 56 sw $t0, CONTEXT_OFFSET_F21($a0) 57 57 58 58 mfc1 $t0, $22 59 59 sw $t0, CONTEXT_OFFSET_F22($a0) 60 60 61 61 mfc1 $t0, $23 62 62 sw $t0, CONTEXT_OFFSET_F23($a0) 63 63 64 64 mfc1 $t0, $24 65 65 sw $t0, CONTEXT_OFFSET_F24($a0) 66 66 67 67 mfc1 $t0, $25 68 68 sw $t0, CONTEXT_OFFSET_F25($a0) 69 69 70 70 mfc1 $t0, $26 71 71 sw $t0, CONTEXT_OFFSET_F26($a0) 72 72 73 73 mfc1 $t0, $27 74 74 sw $t0, CONTEXT_OFFSET_F27($a0) 75 75 76 76 mfc1 $t0, $28 77 77 sw $t0, CONTEXT_OFFSET_F28($a0) 78 78 79 79 mfc1 $t0, $29 80 80 sw $t0, CONTEXT_OFFSET_F29($a0) 81 81 82 82 mfc1 $t0, $30 83 83 sw $t0, CONTEXT_OFFSET_F30($a0) 84 84 #endif /* CONFIG_FPU */ 85 85 86 86 sw $ra, CONTEXT_OFFSET_PC($a0) 87 87 sw $sp, CONTEXT_OFFSET_SP($a0) 88 88 89 89 # context_save returns 1 90 90 j $ra … … 104 104 lw $gp, CONTEXT_OFFSET_GP($a0) 105 105 lw $k1, CONTEXT_OFFSET_TLS($a0) 106 106 107 107 #ifdef CONFIG_FPU 108 108 lw $t0, CONTEXT_OFFSET_F20($a0) 109 109 mtc1 $t0, $20 110 110 111 111 lw $t0, CONTEXT_OFFSET_F21($a0) 112 112 mtc1 $t0, $21 113 113 114 114 lw $t0, CONTEXT_OFFSET_F22($a0) 115 115 mtc1 $t0, $22 116 116 117 117 lw $t0, CONTEXT_OFFSET_F23($a0) 118 118 mtc1 $t0, $23 119 119 120 120 lw $t0, CONTEXT_OFFSET_F24($a0) 121 121 mtc1 $t0, $24 122 122 123 123 lw $t0, CONTEXT_OFFSET_F25($a0) 124 124 mtc1 $t0, $25 125 125 126 126 lw $t0, CONTEXT_OFFSET_F26($a0) 127 127 mtc1 $t0, $26 128 128 129 129 lw $t0, CONTEXT_OFFSET_F27($a0) 130 130 mtc1 $t0, $27 131 131 132 132 lw $t0, CONTEXT_OFFSET_F28($a0) 133 133 mtc1 $t0, $28 134 134 135 135 lw $t0, CONTEXT_OFFSET_F29($a0) 136 136 mtc1 $t0, $29 137 137 138 138 lw $t0, CONTEXT_OFFSET_F30($a0) 139 139 mtc1 $t0, $30 140 140 #endif /* CONFIG_FPU */ 141 141 142 142 lw $ra, CONTEXT_OFFSET_PC($a0) 143 143 lw $sp, CONTEXT_OFFSET_SP($a0) 144 144 145 145 # Just for the jump into first function, 146 146 # but one instruction should not bother us 147 147 move $t9, $ra 148 148 149 149 # context_restore returns 0 150 150 j $ra -
uspace/lib/c/arch/mips32/src/syscall.c
r3061bc1 ra35b458 46 46 register sysarg_t __mips_reg_t1 asm("$9") = p6; 47 47 register sysarg_t __mips_reg_v0 asm("$2") = id; 48 48 49 49 asm volatile ( 50 50 "syscall\n" … … 63 63 : "%ra" 64 64 ); 65 65 66 66 return __mips_reg_v0; 67 67 } -
uspace/lib/c/arch/mips32/src/thread_entry.S
r3061bc1 ra35b458 43 43 .frame $sp, ABI_STACK_FRAME, $ra 44 44 .cpload $t9 45 45 46 46 # 47 47 # v0 contains address of uarg. 48 48 # 49 49 add $a0, $v0, 0 50 50 51 51 # Allocate the stack frame. 52 52 addiu $sp, -ABI_STACK_FRAME 53 53 54 54 # Allow PIC code 55 55 .cprestore 16 56 56 57 57 jal __thread_main 58 58 nop 59 59 60 60 # 61 61 # Not reached. -
uspace/lib/c/arch/ppc32/include/libarch/atomic.h
r3061bc1 ra35b458 43 43 { 44 44 atomic_count_t tmp; 45 45 46 46 asm volatile ( 47 47 "1:\n" … … 61 61 { 62 62 atomic_count_t tmp; 63 63 64 64 asm volatile ( 65 65 "1:\n" -
uspace/lib/c/arch/ppc32/include/libarch/tls.h
r3061bc1 ra35b458 48 48 void *tp = tcb; 49 49 tp += PPC_TP_OFFSET + sizeof(tcb_t); 50 50 51 51 asm volatile ( 52 52 "mr %%r2, %0\n" … … 59 59 { 60 60 void * retval; 61 61 62 62 asm volatile ( 63 63 "mr %0, %%r2\n" -
uspace/lib/c/arch/ppc32/src/entry.S
r3061bc1 ra35b458 44 44 stw %r3, 0(%r1) 45 45 stwu %r1, -16(%r1) 46 46 47 47 # Pass the PCB pointer to __main() as the first argument. 48 48 # The first argument is passed in r3. -
uspace/lib/c/arch/ppc32/src/fibril.S
r3061bc1 ra35b458 55 55 stw r30, CONTEXT_OFFSET_R30(r3) 56 56 stw r31, CONTEXT_OFFSET_R31(r3) 57 57 58 58 mflr r4 59 59 stw r4, CONTEXT_OFFSET_PC(r3) 60 60 61 61 mfcr r4 62 62 stw r4, CONTEXT_OFFSET_CR(r3) 63 63 64 64 # context_save returns 1 65 65 li r3, 1 … … 89 89 lwz r30, CONTEXT_OFFSET_R30(r3) 90 90 lwz r31, CONTEXT_OFFSET_R31(r3) 91 91 92 92 lwz r4, CONTEXT_OFFSET_CR(r3) 93 93 mtcr r4 94 94 95 95 lwz r4, CONTEXT_OFFSET_PC(r3) 96 96 mtlr r4 97 97 98 98 # context_restore returns 0 99 99 li r3, 0 -
uspace/lib/c/arch/ppc32/src/syscall.c
r3061bc1 ra35b458 47 47 register sysarg_t __ppc32_reg_r8 asm("8") = p6; 48 48 register sysarg_t __ppc32_reg_r9 asm("9") = id; 49 49 50 50 asm volatile ( 51 51 "sc\n" … … 59 59 "r" (__ppc32_reg_r9) 60 60 ); 61 61 62 62 return __ppc32_reg_r3; 63 63 } -
uspace/lib/c/arch/ppc32/src/thread_entry.S
r3061bc1 ra35b458 30 30 31 31 .text 32 32 33 33 ## User-space thread entry point for all but the first threads. 34 34 # -
uspace/lib/c/arch/riscv64/include/libarch/atomic.h
r3061bc1 ra35b458 51 51 return true; 52 52 } 53 53 54 54 return false; 55 55 } … … 59 59 /* On real hardware the increment has to be done 60 60 as an atomic action. */ 61 61 62 62 val->count++; 63 63 } … … 67 67 /* On real hardware the decrement has to be done 68 68 as an atomic action. */ 69 69 70 70 val->count++; 71 71 } … … 76 76 value and the increment have to be done as a single 77 77 atomic action. */ 78 78 79 79 atomic_count_t prev = val->count; 80 80 81 81 val->count++; 82 82 return prev; … … 88 88 value and the decrement have to be done as a single 89 89 atomic action. */ 90 90 91 91 atomic_count_t prev = val->count; 92 92 93 93 val->count--; 94 94 return prev; -
uspace/lib/c/arch/sparc64/include/libarch/atomic.h
r3061bc1 ra35b458 55 55 atomic_count_t a; 56 56 atomic_count_t b; 57 57 58 58 do { 59 59 volatile uintptr_t ptr = (uintptr_t) &val->count; 60 60 61 61 a = *((atomic_count_t *) ptr); 62 62 b = a + i; 63 63 64 64 asm volatile ( 65 65 "casx %0, %2, %1\n" … … 69 69 ); 70 70 } while (a != b); 71 71 72 72 return a; 73 73 } -
uspace/lib/c/arch/sparc64/include/libarch/syscall.h
r3061bc1 ra35b458 66 66 : "memory" 67 67 ); 68 68 69 69 return a1; 70 70 } -
uspace/lib/c/arch/sparc64/src/entry.S
r3061bc1 ra35b458 45 45 flushw 46 46 add %g0, -0x7ff, %fp 47 47 48 48 # Pass pcb_ptr as the first argument to __main() 49 49 mov %i1, %o0 -
uspace/lib/c/arch/sparc64/src/fibril.S
r3061bc1 ra35b458 68 68 # 69 69 flushw 70 70 71 71 ldx [%o0 + CONTEXT_OFFSET_SP], %sp 72 72 ldx [%o0 + CONTEXT_OFFSET_PC], %o7 -
uspace/lib/c/arch/sparc64/src/thread_entry.S
r3061bc1 ra35b458 30 30 31 31 .text 32 32 33 33 ## User-space thread entry point for all but the first threads. 34 34 # … … 50 50 call __thread_main ! %o0 contains address of uarg 51 51 or %l7, %lo(_gp), %l7 52 52 53 53 ! not reached
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