Changeset a35b458 in mainline for uspace/drv/bus/isa
- Timestamp:
- 2018-03-02T20:10:49Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- Location:
- uspace/drv/bus/isa
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/isa/i8237.c
r3061bc1 ra35b458 99 99 uint8_t channel_start3; 100 100 uint8_t channel_count3; 101 101 102 102 uint8_t command_status; 103 103 104 104 /** Memory to memory transfers, NOT implemented on PCs */ 105 105 uint8_t request; … … 107 107 uint8_t mode; 108 108 uint8_t flip_flop; 109 109 110 110 /* 111 111 * Master reset sets Flip-Flop low, clears status, … … 136 136 uint8_t reserved6; 137 137 uint8_t channel_count7; 138 138 139 139 uint8_t command_status; 140 140 uint8_t reserved8; … … 230 230 .flip_flop_address = (uint8_t *) 0x0c, 231 231 }, 232 232 233 233 /* The second chip 16-bit */ 234 234 { /* Channel 4 - Unusable */ … … 265 265 }, 266 266 }, 267 267 268 268 .page_table = NULL, 269 269 .first = NULL, … … 286 286 if (ret != EOK) 287 287 return EIO; 288 288 289 289 ret = pio_enable(DMA_CONTROLLER_FIRST_BASE, 290 290 sizeof(dma_controller_regs_first_t), (void **) &controller->first); 291 291 if (ret != EOK) 292 292 return EIO; 293 293 294 294 ret = pio_enable(DMA_CONTROLLER_SECOND_BASE, 295 295 sizeof(dma_controller_regs_second_t), (void **) &controller->second); 296 296 if (ret != EOK) 297 297 return EIO; 298 298 299 299 controller->initialized = true; 300 300 301 301 /* Reset the controller */ 302 302 pio_write_8(&controller->second->master_reset, 0xff); 303 303 pio_write_8(&controller->first->master_reset, 0xff); 304 304 305 305 return EOK; 306 306 } … … 347 347 if ((channel == 0) || (channel == 4)) 348 348 return ENOTSUP; 349 349 350 350 /* DMA is limited to 24bit addresses. */ 351 351 if (pa >= (1 << 24)) 352 352 return EINVAL; 353 353 354 354 /* 8 bit channels use only 4 bits from the page register. */ 355 355 if (is_dma8(channel) && (pa >= (1 << 20))) … … 359 359 if ((pa & 0xffff0000) != ((pa + size - 1) & 0xffff0000)) 360 360 return EINVAL; 361 361 362 362 fibril_mutex_lock(&guard); 363 363 364 364 if (!controller_8237.initialized) 365 365 dma_controller_init(&controller_8237); 366 366 367 367 if (!controller_8237.initialized) { 368 368 fibril_mutex_unlock(&guard); 369 369 return EIO; 370 370 } 371 371 372 372 /* 16 bit transfers are a bit special */ 373 373 ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu32 ")", … … 384 384 pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000); 385 385 } 386 386 387 387 const dma_channel_t dma_channel = controller_8237.channels[channel]; 388 388 389 389 ddf_msg(LVL_DEBUG, "Setting channel %u to address %#" PRIx32 " " 390 390 "(size %" PRIu32 "), mode %hhx.", channel, pa, size, mode); 391 391 392 392 /* Mask DMA request */ 393 393 uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) | 394 394 DMA_SINGLE_MASK_MASKED_FLAG; 395 395 pio_write_8(dma_channel.single_mask_address, value); 396 396 397 397 /* Set mode */ 398 398 value = DMA_MODE_CHAN_TO_REG(channel) | mode; … … 400 400 dma_channel.mode_address, value); 401 401 pio_write_8(dma_channel.mode_address, value); 402 402 403 403 /* Set address - reset flip-flop */ 404 404 pio_write_8(dma_channel.flip_flop_address, 0); 405 405 406 406 /* Low byte */ 407 407 value = pa & 0xff; … … 409 409 dma_channel.offset_reg_address, value); 410 410 pio_write_8(dma_channel.offset_reg_address, value); 411 411 412 412 /* High byte */ 413 413 value = (pa >> 8) & 0xff; … … 415 415 dma_channel.offset_reg_address, value); 416 416 pio_write_8(dma_channel.offset_reg_address, value); 417 417 418 418 /* Page address - third byte */ 419 419 value = (pa >> 16) & 0xff; … … 421 421 dma_channel.page_reg_address, value); 422 422 pio_write_8(dma_channel.page_reg_address, value); 423 423 424 424 /* Set size - reset flip-flop */ 425 425 pio_write_8(dma_channel.flip_flop_address, 0); 426 426 427 427 /* Low byte */ 428 428 value = (size - 1) & 0xff; … … 430 430 dma_channel.size_reg_address, value); 431 431 pio_write_8(dma_channel.size_reg_address, value); 432 432 433 433 /* High byte */ 434 434 value = ((size - 1) >> 8) & 0xff; … … 436 436 dma_channel.size_reg_address, value); 437 437 pio_write_8(dma_channel.size_reg_address, value); 438 438 439 439 /* Unmask DMA request */ 440 440 value = DMA_SINGLE_MASK_CHAN_TO_REG(channel); 441 441 pio_write_8(dma_channel.single_mask_address, value); 442 442 443 443 fibril_mutex_unlock(&guard); 444 444 445 445 return EOK; 446 446 } … … 459 459 if (!is_dma8(channel) && !is_dma16(channel)) 460 460 return ENOENT; 461 461 462 462 if ((channel == 0) || (channel == 4)) 463 463 return ENOTSUP; 464 464 465 465 fibril_mutex_lock(&guard); 466 466 if (!controller_8237.initialized) { … … 472 472 /* Get size - reset flip-flop */ 473 473 pio_write_8(dma_channel.flip_flop_address, 0); 474 474 475 475 /* Low byte */ 476 476 const uint8_t value_low = pio_read_8(dma_channel.size_reg_address); 477 477 ddf_msg(LVL_DEBUG2, "Read size low byte: %p:%x.", 478 478 dma_channel.size_reg_address, value_low); 479 479 480 480 /* High byte */ 481 481 const uint8_t value_high = pio_read_8(dma_channel.size_reg_address); -
uspace/drv/bus/isa/isa.c
r3061bc1 ra35b458 402 402 size_t count = fun->hw_resources.count; 403 403 hw_resource_t *resources = fun->hw_resources.resources; 404 404 405 405 if (count < ISA_MAX_HW_RES) { 406 406 if ((dma > 0) && (dma < 4)) { 407 407 resources[count].type = DMA_CHANNEL_8; 408 408 resources[count].res.dma_channel.dma8 = dma; 409 409 410 410 fun->hw_resources.count++; 411 411 ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma, 412 412 ddf_fun_get_name(fun->fnode)); 413 413 414 414 return; 415 415 } … … 418 418 resources[count].type = DMA_CHANNEL_16; 419 419 resources[count].res.dma_channel.dma16 = dma; 420 420 421 421 fun->hw_resources.count++; 422 422 ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma, 423 423 ddf_fun_get_name(fun->fnode)); 424 424 425 425 return; 426 426 } 427 427 428 428 ddf_msg(LVL_WARN, "Skipped dma 0x%x for function %s", dma, 429 429 ddf_fun_get_name(fun->fnode)); … … 492 492 { 493 493 char *end = NULL; 494 494 495 495 val = skip_spaces(val); 496 496 const int dma = strtol(val, &end, 10); 497 497 498 498 if (val != end) 499 499 isa_fun_add_dma(fun, dma); … … 733 733 if (rc != EOK) 734 734 return rc; 735 735 736 736 rc = pio_window_get(sess, &isa->pio_win); 737 737 if (rc != EOK) {
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