Changeset a35b458 in mainline for uspace/drv/bus/isa


Ignore:
Timestamp:
2018-03-02T20:10:49Z (8 years ago)
Author:
Jiří Zárevúcky <zarevucky.jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f1380b7
Parents:
3061bc1
git-author:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
git-committer:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
Message:

style: Remove trailing whitespace on _all_ lines, including empty ones, for particular file types.

Command used: tools/srepl '\s\+$' '' -- *.c *.h *.py *.sh *.s *.S *.ag

Currently, whitespace on empty lines is very inconsistent.
There are two basic choices: Either remove the whitespace, or keep empty lines
indented to the level of surrounding code. The former is AFAICT more common,
and also much easier to do automatically.

Alternatively, we could write script for automatic indentation, and use that
instead. However, if such a script exists, it's possible to use the indented
style locally, by having the editor apply relevant conversions on load/save,
without affecting remote repository. IMO, it makes more sense to adopt
the simpler rule.

Location:
uspace/drv/bus/isa
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/isa/i8237.c

    r3061bc1 ra35b458  
    9999        uint8_t channel_start3;
    100100        uint8_t channel_count3;
    101        
     101
    102102        uint8_t command_status;
    103        
     103
    104104        /** Memory to memory transfers, NOT implemented on PCs */
    105105        uint8_t request;
     
    107107        uint8_t mode;
    108108        uint8_t flip_flop;
    109        
     109
    110110        /*
    111111         * Master reset sets Flip-Flop low, clears status,
     
    136136        uint8_t reserved6;
    137137        uint8_t channel_count7;
    138        
     138
    139139        uint8_t command_status;
    140140        uint8_t reserved8;
     
    230230                        .flip_flop_address = (uint8_t *) 0x0c,
    231231                },
    232                
     232
    233233                /* The second chip 16-bit */
    234234                { /* Channel 4 - Unusable */
     
    265265                },
    266266        },
    267        
     267
    268268        .page_table = NULL,
    269269        .first = NULL,
     
    286286        if (ret != EOK)
    287287                return EIO;
    288        
     288
    289289        ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
    290290            sizeof(dma_controller_regs_first_t), (void **) &controller->first);
    291291        if (ret != EOK)
    292292                return EIO;
    293        
     293
    294294        ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
    295295                sizeof(dma_controller_regs_second_t), (void **) &controller->second);
    296296        if (ret != EOK)
    297297                return EIO;
    298        
     298
    299299        controller->initialized = true;
    300        
     300
    301301        /* Reset the controller */
    302302        pio_write_8(&controller->second->master_reset, 0xff);
    303303        pio_write_8(&controller->first->master_reset, 0xff);
    304        
     304
    305305        return EOK;
    306306}
     
    347347        if ((channel == 0) || (channel == 4))
    348348                return ENOTSUP;
    349        
     349
    350350        /* DMA is limited to 24bit addresses. */
    351351        if (pa >= (1 << 24))
    352352                return EINVAL;
    353        
     353
    354354        /* 8 bit channels use only 4 bits from the page register. */
    355355        if (is_dma8(channel) && (pa >= (1 << 20)))
     
    359359        if ((pa & 0xffff0000) != ((pa + size - 1) & 0xffff0000))
    360360                return EINVAL;
    361        
     361
    362362        fibril_mutex_lock(&guard);
    363        
     363
    364364        if (!controller_8237.initialized)
    365365                dma_controller_init(&controller_8237);
    366        
     366
    367367        if (!controller_8237.initialized) {
    368368                fibril_mutex_unlock(&guard);
    369369                return EIO;
    370370        }
    371        
     371
    372372        /* 16 bit transfers are a bit special */
    373373        ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu32 ")",
     
    384384                pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
    385385        }
    386        
     386
    387387        const dma_channel_t dma_channel = controller_8237.channels[channel];
    388        
     388
    389389        ddf_msg(LVL_DEBUG, "Setting channel %u to address %#" PRIx32 " "
    390390            "(size %" PRIu32 "), mode %hhx.", channel, pa, size, mode);
    391        
     391
    392392        /* Mask DMA request */
    393393        uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) |
    394394            DMA_SINGLE_MASK_MASKED_FLAG;
    395395        pio_write_8(dma_channel.single_mask_address, value);
    396        
     396
    397397        /* Set mode */
    398398        value = DMA_MODE_CHAN_TO_REG(channel) | mode;
     
    400400            dma_channel.mode_address, value);
    401401        pio_write_8(dma_channel.mode_address, value);
    402        
     402
    403403        /* Set address - reset flip-flop */
    404404        pio_write_8(dma_channel.flip_flop_address, 0);
    405        
     405
    406406        /* Low byte */
    407407        value = pa & 0xff;
     
    409409            dma_channel.offset_reg_address, value);
    410410        pio_write_8(dma_channel.offset_reg_address, value);
    411        
     411
    412412        /* High byte */
    413413        value = (pa >> 8) & 0xff;
     
    415415            dma_channel.offset_reg_address, value);
    416416        pio_write_8(dma_channel.offset_reg_address, value);
    417        
     417
    418418        /* Page address - third byte */
    419419        value = (pa >> 16) & 0xff;
     
    421421            dma_channel.page_reg_address, value);
    422422        pio_write_8(dma_channel.page_reg_address, value);
    423        
     423
    424424        /* Set size - reset flip-flop */
    425425        pio_write_8(dma_channel.flip_flop_address, 0);
    426        
     426
    427427        /* Low byte */
    428428        value = (size - 1) & 0xff;
     
    430430            dma_channel.size_reg_address, value);
    431431        pio_write_8(dma_channel.size_reg_address, value);
    432        
     432
    433433        /* High byte */
    434434        value = ((size - 1) >> 8) & 0xff;
     
    436436            dma_channel.size_reg_address, value);
    437437        pio_write_8(dma_channel.size_reg_address, value);
    438        
     438
    439439        /* Unmask DMA request */
    440440        value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
    441441        pio_write_8(dma_channel.single_mask_address, value);
    442        
     442
    443443        fibril_mutex_unlock(&guard);
    444        
     444
    445445        return EOK;
    446446}
     
    459459        if (!is_dma8(channel) && !is_dma16(channel))
    460460                return ENOENT;
    461        
     461
    462462        if ((channel == 0) || (channel == 4))
    463463                return ENOTSUP;
    464        
     464
    465465        fibril_mutex_lock(&guard);
    466466        if (!controller_8237.initialized) {
     
    472472        /* Get size - reset flip-flop */
    473473        pio_write_8(dma_channel.flip_flop_address, 0);
    474        
     474
    475475        /* Low byte */
    476476        const uint8_t value_low = pio_read_8(dma_channel.size_reg_address);
    477477        ddf_msg(LVL_DEBUG2, "Read size low byte: %p:%x.",
    478478            dma_channel.size_reg_address, value_low);
    479        
     479
    480480        /* High byte */
    481481        const uint8_t value_high = pio_read_8(dma_channel.size_reg_address);
  • uspace/drv/bus/isa/isa.c

    r3061bc1 ra35b458  
    402402        size_t count = fun->hw_resources.count;
    403403        hw_resource_t *resources = fun->hw_resources.resources;
    404        
     404
    405405        if (count < ISA_MAX_HW_RES) {
    406406                if ((dma > 0) && (dma < 4)) {
    407407                        resources[count].type = DMA_CHANNEL_8;
    408408                        resources[count].res.dma_channel.dma8 = dma;
    409                        
     409
    410410                        fun->hw_resources.count++;
    411411                        ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma,
    412412                            ddf_fun_get_name(fun->fnode));
    413                        
     413
    414414                        return;
    415415                }
     
    418418                        resources[count].type = DMA_CHANNEL_16;
    419419                        resources[count].res.dma_channel.dma16 = dma;
    420                        
     420
    421421                        fun->hw_resources.count++;
    422422                        ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma,
    423423                            ddf_fun_get_name(fun->fnode));
    424                        
     424
    425425                        return;
    426426                }
    427                
     427
    428428                ddf_msg(LVL_WARN, "Skipped dma 0x%x for function %s", dma,
    429429                    ddf_fun_get_name(fun->fnode));
     
    492492{
    493493        char *end = NULL;
    494        
     494
    495495        val = skip_spaces(val);
    496496        const int dma = strtol(val, &end, 10);
    497        
     497
    498498        if (val != end)
    499499                isa_fun_add_dma(fun, dma);
     
    733733        if (rc != EOK)
    734734                return rc;
    735        
     735
    736736        rc = pio_window_get(sess, &isa->pio_win);
    737737        if (rc != EOK) {
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