Changes in kernel/arch/sparc64/src/sun4u/start.S [1b20da0:a35b458] in mainline

File:

• kernel/arch/sparc64/src/sun4u/start.S (modified) (13 diffs)

kernel/arch/sparc64/src/sun4u/start.S

@@ -85 +85 @@
         ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
         srlx %l6, 13, %l5
-        
+
         ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
         sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
@@ -101 +101 @@
         wrpr %g0, NWINDOWS - 1, %cleanwin       ! prevent needless clean_window
                                                 ! traps for kernel
-                                                
+
         wrpr %g0, 0, %wstate                    ! use default spill/fill trap
 
@@ -132 +132 @@
         set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \
                 TLB_DEMAP_CONTEXT_SHIFT), %r1
-        
+
         ! demap context 0
         SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
@@ -161 +161 @@
         sllx %r2, TTE_V_SHIFT, %r2; \
         or %r1, %r2, %r1;
-        
+
         ! write DTLB data and install the kernel mapping
         SET_TLB_DATA(g1, g2, TTE_L | TTE_W)     ! use non-global mapping
@@ -182 +182 @@
         stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
         membar #Sync
-        
+
         /*
          * Now is time to take over the IMMU. Unfortunatelly, it cannot be done
@@ -202 +202 @@
          * the taken over DTLB.
          */
-        
+
         set kernel_image_start, %g5
-        
+
         ! write ITLB tag of context 1
         SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
@@ -215 +215 @@
         stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
         flush %g5
-        
+
         ! switch to context 1
         mov MEM_CONTEXT_TEMP, %g1
         stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
         flush %g5
-        
+
         ! demap context 0
         SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
         stxa %g0, [%g1] ASI_IMMU_DEMAP
         flush %g5
-        
+
         ! write ITLB tag of context 0
         SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
@@ -244 +244 @@
         stxa %g0, [%g1] ASI_IMMU_DEMAP
         flush %g5
-        
+
         ! set context 0 in the primary context register
         stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
         flush %g5
-        
+
         ! leave nucleus - using primary context, i.e. context 0
         wrpr %g0, 0, %tl
@@ -271 +271 @@
         or %l3, %l5, %l3
         stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
-        
+
         ! flush the whole D-cache
         set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1
         stxa %g0, [%g1] ASI_DCACHE_TAG
-        
+
 0:
         membar #Sync
@@ -282 +282 @@
         stxa %g0, [%g1] ASI_DCACHE_TAG
         membar #Sync
-        
+
         /*
          * So far, we have not touched the stack.
@@ -290 +290 @@
         or %sp, %lo(temporary_boot_stack), %sp
         sub %sp, STACK_BIAS, %sp
-        
+
         /*
          * Call sparc64_pre_main(bootinfo)
@@ -296 +296 @@
         call sparc64_pre_main
         mov %o1, %o0
-        
+
         /*
          * Create the first stack frame.
@@ -372 +372 @@
         /* Not reached. */
 #endif
-        
+
 0:
         ba,a %xcc, 0b