Changes in kernel/arch/ppc32/src/asm.S [b66cc97:a35b458] in mainline

File:

• kernel/arch/ppc32/src/asm.S (modified) (7 diffs)

kernel/arch/ppc32/src/asm.S

@@ -40 +40 @@
          * r5 = entry
          */
-        
+
         /* Disable interrupts */
-        
+
         mfmsr r31
         rlwinm r31, r31, 0, 17, 15
         mtmsr r31
         isync
-        
+
         /* Set entry point */
-        
+
         mtsrr0 r5
-        
+
         /* Set privileged state, enable interrupts */
-        
+
         ori r31, r31, MSR_PR
         ori r31, r31, MSR_EE
         mtsrr1 r31
-        
+
         /* Set stack */
-        
+
         mr sp, r4
-        
+
         /* %r6 is defined to hold pcb_ptr - set it to 0 */
-        
+
         xor r6, r6, r6
-        
+
         /* Jump to userspace */
-        
+
         rfi
 FUNCTION_END(userspace_asm)
@@ -73 +73 @@
 SYMBOL(iret)
         /* Disable interrupts */
-        
+
         mfmsr r31
         rlwinm r31, r31, 0, 17, 15
         mtmsr r31
         isync
-        
+
         lwz r0, ISTATE_OFFSET_R0(sp)
         lwz r2, ISTATE_OFFSET_R2(sp)
@@ -109 +109 @@
         lwz r30, ISTATE_OFFSET_R30(sp)
         lwz r31, ISTATE_OFFSET_R31(sp)
-        
+
         lwz r12, ISTATE_OFFSET_CR(sp)
         mtcr r12
-        
+
         lwz r12, ISTATE_OFFSET_PC(sp)
         mtsrr0 r12
-        
+
         lwz r12, ISTATE_OFFSET_SRR1(sp)
         mtsrr1 r12
-        
+
         lwz r12, ISTATE_OFFSET_LR(sp)
         mtlr r12
-        
+
         lwz r12, ISTATE_OFFSET_CTR(sp)
         mtctr r12
-        
+
         lwz r12, ISTATE_OFFSET_XER(sp)
         mtxer r12
-        
+
         lwz r12, ISTATE_OFFSET_R12(sp)
         lwz sp, ISTATE_OFFSET_SP(sp)
-        
+
         rfi
 
 SYMBOL(iret_syscall)
         /* Disable interrupts */
-        
+
         mfmsr r31
         rlwinm r31, r31, 0, 17, 15
         mtmsr r31
         isync
-        
+
         lwz r0, ISTATE_OFFSET_R0(sp)
         lwz r2, ISTATE_OFFSET_R2(sp)
@@ -170 +170 @@
         lwz r30, ISTATE_OFFSET_R30(sp)
         lwz r31, ISTATE_OFFSET_R31(sp)
-        
+
         lwz r12, ISTATE_OFFSET_CR(sp)
         mtcr r12
-        
+
         lwz r12, ISTATE_OFFSET_PC(sp)
         mtsrr0 r12
-        
+
         lwz r12, ISTATE_OFFSET_SRR1(sp)
         mtsrr1 r12
-        
+
         lwz r12, ISTATE_OFFSET_LR(sp)
         mtlr r12
-        
+
         lwz r12, ISTATE_OFFSET_CTR(sp)
         mtctr r12
-        
+
         lwz r12, ISTATE_OFFSET_XER(sp)
         mtxer r12
-        
+
         lwz r12, ISTATE_OFFSET_R12(sp)
         lwz sp, ISTATE_OFFSET_SP(sp)
-        
+
         rfi
 
@@ -200 +200 @@
         addi r4, r4, -4
         beq 2f
-        
+
         andi. r0, r6, 3
         mtctr r7
         bne 5f
-        
+
         1:
-        
+
                 lwz r7, 4(r4)
                 lwzu r8, 8(r4)
@@ -212 +212 @@
                 stwu r8, 8(r6)
                 bdnz 1b
-                
+
                 andi. r5, r5, 7
-        
+
         2:
-        
+
                 cmplwi 0, r5, 4
                 blt 3f
-                
+
                 lwzu r0, 4(r4)
                 addi r5, r5, -4
                 stwu r0, 4(r6)
-        
+
         3:
-        
+
                 cmpwi 0, r5, 0
                 beqlr
@@ -231 +231 @@
                 addi r4, r4, 3
                 addi r6, r6, 3
-        
+
         4:
-        
+
                 lbzu r0, 1(r4)
                 stbu r0, 1(r6)
                 bdnz 4b
                 blr
-        
+
         5:
-        
+
                 subfic r0, r0, 4
                 mtctr r0
-        
+
         6:
-        
+
                 lbz r7, 4(r4)
                 addi r4, r4, 1