Changeset a35b458 in mainline for kernel/arch/mips32/src/mm
- Timestamp:
- 2018-03-02T20:10:49Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- Location:
- kernel/arch/mips32/src/mm
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/mips32/src/mm/frame.c
r3061bc1 ra35b458 82 82 if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH)) 83 83 return false; 84 84 85 85 /* MSIM device (dkeyboard) */ 86 86 if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH)) … … 92 92 return false; 93 93 #endif 94 94 95 95 return true; 96 96 } … … 108 108 if ((frame << ZERO_PAGE_WIDTH) < KA2PA(config.base)) 109 109 return false; 110 110 111 111 /* Kernel */ 112 112 if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, 113 113 KA2PA(config.base), config.kernel_size)) 114 114 return false; 115 115 116 116 /* Kernel stack */ 117 117 if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, 118 118 KA2PA(config.stack_base), config.stack_size)) 119 119 return false; 120 120 121 121 /* Init tasks */ 122 122 bool safe = true; … … 128 128 break; 129 129 } 130 130 131 131 return safe; 132 132 } … … 161 161 ZONE_AVAILABLE | ZONE_HIGHMEM); 162 162 } 163 163 164 164 if (phys_regions_count < MAX_REGIONS) { 165 165 phys_regions[phys_regions_count].start = first; … … 182 182 { 183 183 ipl_t ipl = interrupts_disable(); 184 184 185 185 /* Clear and initialize TLB */ 186 186 cp0_pagemask_write(ZERO_PAGE_MASK); … … 194 194 tlbwi(); 195 195 } 196 196 197 197 pfn_t start_frame = 0; 198 198 pfn_t frame; 199 199 bool avail = true; 200 200 201 201 /* Walk through all 1 MB frames */ 202 202 for (frame = 0; frame < ZERO_FRAMES; frame++) { … … 211 211 tlb_prepare_entry_lo(&lo1, false, false, false, false, 0); 212 212 tlb_prepare_entry_hi(&hi, ZERO_PAGE_ASID, ZERO_PAGE_ADDR); 213 213 214 214 cp0_pagemask_write(ZERO_PAGE_MASK); 215 215 cp0_entry_lo0_write(lo0.value); … … 218 218 cp0_index_write(ZERO_PAGE_TLBI); 219 219 tlbwi(); 220 220 221 221 ZERO_PAGE_VALUE = 0; 222 222 if (ZERO_PAGE_VALUE != 0) … … 229 229 } 230 230 } 231 231 232 232 if (!avail) { 233 233 frame_add_region(start_frame, frame, true); … … 236 236 } 237 237 } 238 238 239 239 frame_add_region(start_frame, frame, true); 240 240 241 241 /* Blacklist interrupt vector frame */ 242 242 frame_mark_unavailable(0, 1); … … 267 267 frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE); 268 268 #endif 269 269 270 270 /* Cleanup */ 271 271 cp0_pagemask_write(ZERO_PAGE_MASK); … … 275 275 cp0_index_write(ZERO_PAGE_TLBI); 276 276 tlbwi(); 277 277 278 278 interrupts_restore(ipl); 279 279 } … … 286 286 { 287 287 printf("[base ] [size ]\n"); 288 288 289 289 size_t i; 290 290 for (i = 0; i < phys_regions_count; i++) { -
kernel/arch/mips32/src/mm/tlb.c
r3061bc1 ra35b458 76 76 77 77 /* Clear and initialize TLB. */ 78 78 79 79 for (i = 0; i < TLB_ENTRY_COUNT; i++) { 80 80 cp0_index_write(i); 81 81 tlbwi(); 82 82 } 83 83 84 84 /* 85 85 * The kernel is going to make use of some wired … … 98 98 uintptr_t badvaddr; 99 99 pte_t pte; 100 100 101 101 badvaddr = cp0_badvaddr_read(); 102 102 … … 291 291 lo1_save.value = cp0_entry_lo1_read(); 292 292 mask_save.value = cp0_pagemask_read(); 293 293 294 294 printf("[nr] [asid] [vpn2 ] [mask] [gvdc] [pfn ]\n"); 295 295 296 296 for (i = 0; i < TLB_ENTRY_COUNT; i++) { 297 297 cp0_index_write(i); 298 298 tlbr(); 299 299 300 300 mask.value = cp0_pagemask_read(); 301 301 hi.value = cp0_entry_hi_read(); 302 302 lo0.value = cp0_entry_lo0_read(); 303 303 lo1.value = cp0_entry_lo1_read(); 304 304 305 305 printf("%-4u %-6u %0#10x %-#6x %1u%1u%1u%1u %0#10x\n", 306 306 i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask, … … 309 309 lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn)); 310 310 } 311 311 312 312 cp0_entry_hi_write(hi_save.value); 313 313 cp0_entry_lo0_write(lo0_save.value); … … 339 339 cp0_entry_lo0_write(lo0.value); 340 340 cp0_entry_lo1_write(lo1.value); 341 341 342 342 tlbwi(); 343 343 } 344 344 345 345 cp0_entry_hi_write(hi_save.value); 346 346 } … … 360 360 361 361 hi_save.value = cp0_entry_hi_read(); 362 362 363 363 for (i = 0; i < TLB_ENTRY_COUNT; i++) { 364 364 cp0_index_write(i); 365 365 tlbr(); 366 366 367 367 hi.value = cp0_entry_hi_read(); 368 368 369 369 if (hi.asid == asid) { 370 370 lo0.value = cp0_entry_lo0_read(); … … 380 380 } 381 381 } 382 382 383 383 cp0_entry_hi_write(hi_save.value); 384 384 } … … 399 399 400 400 assert(interrupts_disabled()); 401 401 402 402 if (asid == ASID_INVALID) 403 403 return; … … 431 431 } 432 432 } 433 433 434 434 cp0_entry_hi_write(hi_save.value); 435 435 }
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