Changes in kernel/arch/ia64/src/mm/tlb.c [1b20da0:a35b458] in mainline

File:

• kernel/arch/ia64/src/mm/tlb.c (modified) (35 diffs)

kernel/arch/ia64/src/mm/tlb.c

@@ -61 +61 @@
         uintptr_t adr;
         uint32_t count1, count2, stride1, stride2;
-        
+
         unsigned int i, j;
-        
+
         adr = PAL_PTCE_INFO_BASE();
         count1 = PAL_PTCE_INFO_COUNT1();
@@ -69 +69 @@
         stride1 = PAL_PTCE_INFO_STRIDE1();
         stride2 = PAL_PTCE_INFO_STRIDE2();
-        
+
         ipl = interrupts_disable();
-        
+
         for (i = 0; i < count1; i++) {
                 for (j = 0; j < count2; j++) {
@@ -82 +82 @@
                 adr += stride1;
         }
-        
+
         interrupts_restore(ipl);
-        
+
         srlz_d();
         srlz_i();
-        
+
 #ifdef CONFIG_VHPT
         vhpt_invalidate_all();
@@ -110 +110 @@
         int b = 0;
         int c = cnt;
-        
+
         uintptr_t va;
         va = page;
-        
+
         rr.word = rr_read(VA2VRN(page));
         if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) {
@@ -121 +121 @@
                  */
                 region_register_t rr0;
-                
+
                 rr0 = rr;
                 rr0.map.rid = ASID2RID(asid, VA2VRN(page));
@@ -128 +128 @@
                 srlz_i();
         }
-        
+
         while (c >>= 1)
                 b++;
         b >>= 1;
         uint64_t ps;
-        
+
         switch (b) {
         case 0: /* cnt 1 - 3 */
@@ -172 +172 @@
                 break;
         }
-        
+
         for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps))
                 asm volatile (
@@ -179 +179 @@
                            [ps] "r" (ps << 2)
                 );
-        
+
         srlz_d();
         srlz_i();
-        
+
         if (restore_rr) {
                 rr_write(VA2VRN(page), rr.word);
@@ -229 +229 @@
         region_register_t rr;
         bool restore_rr = false;
-        
+
         rr.word = rr_read(VA2VRN(va));
         if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -237 +237 @@
                  */
                 region_register_t rr0;
-                
+
                 rr0 = rr;
                 rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -244 +244 @@
                 srlz_i();
         }
-        
+
         asm volatile (
                 "mov r8 = psr ;;\n"
@@ -264 +264 @@
                 : "p6", "p7", "r8"
         );
-        
+
         if (restore_rr) {
                 rr_write(VA2VRN(va), rr.word);
@@ -316 +316 @@
         region_register_t rr;
         bool restore_rr = false;
-        
+
         rr.word = rr_read(VA2VRN(va));
         if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -324 +324 @@
                  */
                 region_register_t rr0;
-                
+
                 rr0 = rr;
                 rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -331 +331 @@
                 srlz_i();
         }
-        
+
         asm volatile (
                 "mov r8 = psr ;;\n"
@@ -352 +352 @@
                 : "p6", "p7", "r8"
         );
-        
+
         if (restore_rr) {
                 rr_write(VA2VRN(va), rr.word);
@@ -373 +373 @@
 {
         tlb_entry_t entry;
-        
+
         entry.word[0] = 0;
         entry.word[1] = 0;
-        
+
         entry.p = true;           /* present */
         entry.ma = MA_WRITEBACK;
@@ -385 +385 @@
         entry.ppn = frame >> PPN_SHIFT;
         entry.ps = PAGE_WIDTH;
-        
+
         if (dtr)
                 dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
@@ -418 +418 @@
 {
         tlb_entry_t entry;
-        
+
         entry.word[0] = 0;
         entry.word[1] = 0;
-        
+
         entry.p = t->p;
         entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
@@ -430 +430 @@
         entry.ppn = t->frame >> PPN_SHIFT;
         entry.ps = PAGE_WIDTH;
-        
+
         dtc_mapping_insert(t->page, t->as->asid, entry);
-        
+
 #ifdef CONFIG_VHPT
         vhpt_mapping_insert(t->page, t->as->asid, entry);
@@ -446 +446 @@
 {
         tlb_entry_t entry;
-        
+
         entry.word[0] = 0;
         entry.word[1] = 0;
-        
+
         assert(t->x);
-        
+
         entry.p = t->p;
         entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
@@ -459 +459 @@
         entry.ppn = t->frame >> PPN_SHIFT;
         entry.ps = PAGE_WIDTH;
-        
+
         itc_mapping_insert(t->page, t->as->asid, entry);
-        
+
 #ifdef CONFIG_VHPT
         vhpt_mapping_insert(t->page, t->as->asid, entry);
@@ -486 +486 @@
         uintptr_t va;
         pte_t t;
-        
+
         va = istate->cr_ifa; /* faulting address */
-        
+
         assert(!is_kernel_fault(va));
 
@@ -532 +532 @@
                         uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >>
                             LEGACYIO_SINGLE_PAGE_WIDTH;
-                        
+
                         if (is_io_page_accessible(io_page)) {
                                 uint64_t page, frame;
-                                
+
                                 page = LEGACYIO_USER_BASE +
                                     (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page;
                                 frame = LEGACYIO_PHYS_BASE +
                                     (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page;
-                                
+
                                 tlb_entry_t entry;
-                                
+
                                 entry.word[0] = 0;
                                 entry.word[1] = 0;
-                                
+
                                 entry.p = true;             /* present */
                                 entry.ma = MA_UNCACHEABLE;
@@ -554 +554 @@
                                 entry.ppn = frame >> PPN_SHIFT;
                                 entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH;
-                                
+
                                 dtc_mapping_insert(page, TASK->as->asid, entry);
                                 return 1;
@@ -563 +563 @@
                 }
         }
-        
+
         return 0;
 }
@@ -586 +586 @@
                 return;
         }
-        
+
         uintptr_t va = istate->cr_ifa;  /* faulting address */
         as_t *as = AS;
-        
+
         if (is_kernel_fault(va)) {
                 if (va < end_of_identity) {
@@ -601 +601 @@
                 }
         }
-        
-        
+
+
         pte_t t;
         bool found = page_mapping_find(as, va, true, &t);
@@ -616 +616 @@
                 if (try_memmap_io_insertion(va, istate))
                         return;
-                
+
                 /*
                  * Forward the page fault to the address space page fault
@@ -649 +649 @@
         pte_t t;
         as_t *as = AS;
-        
+
         va = istate->cr_ifa;  /* faulting address */
-        
+
         if (is_kernel_fault(va))
                 as = AS_KERNEL;
@@ -683 +683 @@
         uintptr_t va;
         pte_t t;
-        
+
         va = istate->cr_ifa;  /* faulting address */
 
         assert(!is_kernel_fault(va));
-        
+
         bool found = page_mapping_find(AS, va, true, &t);
 
@@ -717 +717 @@
         pte_t t;
         as_t *as = AS;
-        
+
         va = istate->cr_ifa;  /* faulting address */
-        
+
         if (is_kernel_fault(va))
                 as = AS_KERNEL;
@@ -755 +755 @@
         uintptr_t va;
         pte_t t;
-        
+
         va = istate->cr_ifa;  /* faulting address */
 
         assert(!is_kernel_fault(va));
-        
+
         /*
          * Assume a write to a read-only page.
@@ -782 +782 @@
         uintptr_t va;
         pte_t t;
-        
+
         va = istate->cr_ifa;  /* faulting address */
-        
+
         assert(!is_kernel_fault(va));
 
@@ -790 +790 @@
 
         assert(found);
-        
+
         if (t.p) {
                 /*