Changeset a35b458 in mainline for kernel/arch/ia64/src
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- Location:
- kernel/arch/ia64/src
- Files:
-
- 17 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia64/src/asm.S
r3061bc1 ra35b458 46 46 FUNCTION_BEGIN(memcpy_to_uspace) 47 47 alloc loc0 = ar.pfs, 3, 1, 0, 0 48 48 49 49 adds r14 = 7, in1 50 50 mov r2 = ar.lc … … 53 53 cmp.ne p6, p7 = r14, in1 54 54 (p7) br.cond.dpnt 3f ;; 55 55 56 56 0: 57 57 58 58 cmp.ne p6, p7 = 0, in2 59 59 (p7) br.cond.dpnt 2f ;; … … 62 62 (p6) mov r17 = r0 ;; 63 63 (p6) mov ar.lc = r14 64 64 65 65 1: 66 66 67 67 add r14 = r16, in1 68 68 add r15 = r16, in0 … … 72 72 st1 [r15] = r14 73 73 br.cloop.sptk.few 1b ;; 74 74 75 75 2: 76 76 77 77 mov ar.lc = r2 78 78 mov ar.pfs = loc0 79 79 br.ret.sptk.many rp 80 80 81 81 3: 82 82 83 83 adds r14 = 7, in0 ;; 84 84 and r14 = -8, r14 ;; … … 92 92 (p6) mov r17 = r0 ;; 93 93 (p6) mov ar.lc = r14 94 94 95 95 4: 96 96 97 97 shladd r14 = r16, 3, r0 98 98 adds r16 = 1, r17 ;; … … 103 103 st8 [r14] = r15 104 104 br.cloop.sptk.few 4b 105 105 106 106 5: 107 107 108 108 and r15 = 7, in2 109 109 shladd r14 = r18, 3, r0 … … 116 116 (p6) br.cond.dpnt 2b ;; 117 117 mov ar.lc = r15 118 118 119 119 6: 120 120 121 121 add r14 = r16, r17 122 122 add r15 = r16, in0 … … 155 155 FUNCTION_BEGIN(switch_to_userspace) 156 156 alloc loc0 = ar.pfs, 6, 3, 0, 0 157 157 158 158 /* Disable interruption collection and interrupts */ 159 159 rsm (PSR_IC_MASK | PSR_I_MASK) 160 160 srlz.d ;; 161 161 srlz.i ;; 162 162 163 163 mov cr.ipsr = in4 164 164 mov cr.iip = in0 165 165 mov r12 = in1 166 166 167 167 xor r1 = r1, r1 168 168 169 169 /* r2 is defined to hold pcb_ptr - set it to 0 */ 170 170 xor r2 = r2, r2 171 171 172 172 mov loc1 = cr.ifs 173 173 movl loc2 = PFM_MASK ;; 174 174 and loc1 = loc2, loc1 ;; 175 175 mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ 176 176 177 177 invala 178 178 179 179 mov loc1 = ar.rsc ;; 180 180 and loc1 = ~3, loc1 ;; 181 181 mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ 182 182 183 183 flushrs ;; 184 184 185 185 mov ar.bspstore = in2 ;; 186 186 mov ar.rsc = in5 ;; 187 187 188 188 mov r8 = in3 189 189 190 190 rfi ;; 191 191 FUNCTION_END(switch_to_userspace) -
kernel/arch/ia64/src/context.S
r3061bc1 ra35b458 45 45 flushrs 46 46 mov loc4 = ar.bsp 47 47 48 48 /* 49 49 * Put RSE to enforced lazy mode. … … 117 117 118 118 mov loc2 = ar.unat 119 119 120 120 /* 121 121 * Save application registers … … 177 177 178 178 mov ar.unat = loc1 179 179 180 180 add r8 = r0, r0, 1 /* context_save returns 1 */ 181 181 br.ret.sptk.many b0 … … 239 239 ld8 loc5 = [loc14] /* load ar.rnat */ 240 240 ld8 loc6 = [loc15] /* load ar.lc */ 241 241 242 242 .auto 243 243 … … 274 274 mov ar.unat = loc2 ;; 275 275 mov ar.lc = loc6 276 276 277 277 /* 278 278 * Restore general registers including NaT bits … … 332 332 ldf.fill f30 = [loc48] 333 333 ldf.fill f31 = [loc49] 334 334 335 335 mov ar.unat = loc1 336 336 337 337 mov r8 = r0 /* context_restore returns 0 */ 338 338 br.ret.sptk.many b0 -
kernel/arch/ia64/src/cpu/cpu.c
r3061bc1 ra35b458 54 54 const char *family_str; 55 55 char vendor[2 * sizeof(uint64_t) + 1]; 56 56 57 57 memcpy(vendor, &CPU->arch.cpuid0, 8); 58 58 memcpy(vendor + 8, &CPU->arch.cpuid1, 8); 59 59 vendor[sizeof(vendor) - 1] = 0; 60 60 61 61 switch (m->arch.cpuid3.family) { 62 62 case FAMILY_ITANIUM: … … 70 70 break; 71 71 } 72 72 73 73 printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id, 74 74 family_str, vendor, CPU->arch.cpuid3.archrev, -
kernel/arch/ia64/src/ddi/ddi.c
r3061bc1 ra35b458 59 59 if (task->arch.iomap == NULL) 60 60 return ENOMEM; 61 61 62 62 void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0); 63 63 if (store == NULL) 64 64 return ENOMEM; 65 65 66 66 bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store); 67 67 bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES); 68 68 } 69 69 70 70 uintptr_t iopage = ioaddr / PORTS_PER_PAGE; 71 71 size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE); 72 72 bitmap_set_range(task->arch.iomap, iopage, size / 4); 73 73 74 74 return EOK; 75 75 } … … 93 93 size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE); 94 94 bitmap_clear_range(task->arch.iomap, iopage, size / 4); 95 95 96 96 return EOK; 97 97 } -
kernel/arch/ia64/src/drivers/it.c
r3061bc1 ra35b458 68 68 it_irq.handler = it_interrupt; 69 69 irq_register(&it_irq); 70 70 71 71 uint64_t base_freq; 72 72 base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >> … … 75 75 base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >> 76 76 FREQ_DENOMINATOR_SHIFT; 77 77 78 78 it_delta = base_freq / HZ; 79 79 } 80 80 81 81 /* Initialize Interval Timer external interrupt vector */ 82 82 cr_itv_t itv; 83 83 84 84 itv.value = itv_read(); 85 85 itv.vector = INTERRUPT_TIMER; 86 86 itv.m = 0; 87 87 itv_write(itv.value); 88 88 89 89 /* Set Interval Timer Counter to zero */ 90 90 itc_write(0); 91 91 92 92 /* Generate first Interval Timer interrupt in IT_DELTA ticks */ 93 93 itm_write(IT_DELTA); 94 94 95 95 /* Propagate changes */ 96 96 srlz_d(); … … 113 113 { 114 114 eoi_write(EOI); 115 115 116 116 int64_t itm = itm_read(); 117 117 118 118 while (true) { 119 119 int64_t itc = itc_read(); 120 120 itc += IT_SERVICE_CLOCKS; 121 121 122 122 itm += IT_DELTA; 123 123 if (itm - itc < 0) … … 126 126 break; 127 127 } 128 128 129 129 itm_write(itm); 130 130 srlz_d(); /* Propagate changes */ 131 131 132 132 /* 133 133 * We are holding a lock which prevents preemption. -
kernel/arch/ia64/src/drivers/ski.c
r3061bc1 ra35b458 49 49 /** Interval between polling in microseconds */ 50 50 POLL_INTERVAL = 10000, /* 0.01 s */ 51 51 52 52 /** Max. number of characters to pull out at a time */ 53 53 POLL_LIMIT = 30, 54 54 55 55 SKI_INIT_CONSOLE = 20, 56 56 SKI_GETCHAR = 21, … … 82 82 { 83 83 uint64_t ch; 84 84 85 85 asm volatile ( 86 86 "mov r15 = %1\n" 87 87 "break 0x80000;;\n" /* modifies r8 */ 88 88 "mov %0 = r8;;\n" 89 89 90 90 : "=r" (ch) 91 91 : "i" (SKI_GETCHAR) 92 92 : "r15", "r8" 93 93 ); 94 94 95 95 return (wchar_t) ch; 96 96 } … … 103 103 { 104 104 int count = POLL_LIMIT; 105 105 106 106 while (count > 0) { 107 107 wchar_t ch = ski_getchar(); 108 108 109 109 if (ch == '\0') 110 110 break; 111 111 112 112 indev_push_character(instance->srlnin, ch); 113 113 --count; … … 119 119 { 120 120 ski_instance_t *instance = (ski_instance_t *) arg; 121 121 122 122 while (true) { 123 123 // TODO FIXME: … … 126 126 if (console_override) 127 127 poll_keyboard(instance); 128 128 129 129 thread_usleep(POLL_INTERVAL); 130 130 } … … 141 141 if (instance) 142 142 return; 143 143 144 144 asm volatile ( 145 145 "mov r15 = %0\n" … … 149 149 : "r15", "r8" 150 150 ); 151 151 152 152 instance = malloc(sizeof(ski_instance_t), FRAME_ATOMIC); 153 153 154 154 if (instance) { 155 155 instance->thread = thread_create(kskipoll, instance, TASK, 156 156 THREAD_FLAG_UNCOUNTED, "kskipoll"); 157 157 158 158 if (!instance->thread) { 159 159 free(instance); … … 161 161 return; 162 162 } 163 163 164 164 instance->srlnin = NULL; 165 165 } … … 196 196 if (ch == '\n') 197 197 ski_do_putchar('\r'); 198 198 199 199 ski_do_putchar(ch); 200 200 } else … … 208 208 if (!instance) 209 209 return NULL; 210 210 211 211 outdev_t *skidev = malloc(sizeof(outdev_t), FRAME_ATOMIC); 212 212 if (!skidev) 213 213 return NULL; 214 214 215 215 outdev_initialize("skidev", skidev, &skidev_ops); 216 216 skidev->data = instance; 217 217 218 218 if (!fb_exported) { 219 219 /* … … 224 224 sysinfo_set_item_val("fb", NULL, true); 225 225 sysinfo_set_item_val("fb.kind", NULL, 6); 226 226 227 227 fb_exported = true; 228 228 } 229 229 230 230 return skidev; 231 231 } … … 241 241 assert(instance); 242 242 assert(srlnin); 243 243 244 244 instance->srlnin = srlnin; 245 245 thread_ready(instance->thread); 246 246 247 247 sysinfo_set_item_val("kbd", NULL, true); 248 248 sysinfo_set_item_val("kbd.type", NULL, KBD_SKI); -
kernel/arch/ia64/src/fpu_context.c
r3061bc1 ra35b458 103 103 [f61] "=m" (fctx->fr[29]) 104 104 ); 105 105 106 106 asm volatile ( 107 107 "stf.spill %[f62] = f62\n" … … 314 314 [f61] "m" (fctx->fr[29]) 315 315 ); 316 316 317 317 asm volatile ( 318 318 "ldf.fill f62 = %[f62]\n" -
kernel/arch/ia64/src/ia64.c
r3061bc1 ra35b458 108 108 PAGE_WRITE | PAGE_NOT_CACHEABLE); 109 109 int i; 110 110 111 111 int myid, myeid; 112 112 113 113 myid = ia64_get_cpu_id(); 114 114 myeid = ia64_get_cpu_eid(); … … 167 167 } 168 168 } 169 169 170 170 outdev_t *skidev = skiout_init(); 171 171 if (skidev) 172 172 stdout_wire(skidev); 173 173 #endif 174 174 175 175 #ifdef CONFIG_EGA 176 176 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM); … … 178 178 stdout_wire(egadev); 179 179 #endif 180 180 181 181 #ifdef CONFIG_NS16550 182 182 ns16550_instance_t *ns16550_instance … … 191 191 } 192 192 } 193 193 194 194 sysinfo_set_item_val("kbd", NULL, true); 195 195 sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ); … … 198 198 (uintptr_t) NS16550_BASE); 199 199 #endif 200 200 201 201 #ifdef CONFIG_I8042 202 202 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, … … 211 211 } 212 212 #endif 213 213 214 214 sysinfo_set_item_val("ia64_iospace", NULL, true); 215 215 sysinfo_set_item_val("ia64_iospace.address", NULL, true); … … 251 251 kernel_uarg->uspace_stack_size / 2, 252 252 (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value); 253 253 254 254 while (1); 255 255 } … … 274 274 fptr->fnc = (sysarg_t) addr; 275 275 fptr->gp = ((sysarg_t *) caller)[1]; 276 276 277 277 return (void *) fptr; 278 278 } -
kernel/arch/ia64/src/interrupt.c
r3061bc1 ra35b458 124 124 { 125 125 assert(n <= VECTOR_MAX); 126 126 127 127 if (n >= VECTORS_16_BUNDLE_START) 128 128 return vector_names_16_bundle[n - VECTORS_16_BUNDLE_START]; … … 141 141 printf("cr.isr=%#0" PRIx64 "\tcr.ipsr=%#0" PRIx64 "\n", 142 142 istate->cr_isr.value, istate->cr_ipsr.value); 143 143 144 144 printf("cr.iip=%#0" PRIxPTR ", #%u\t(%s)\n", 145 145 istate->cr_iip, istate->cr_isr.ei, … … 154 154 { 155 155 const char *desc; 156 156 157 157 switch (istate->cr_isr.ge_code) { 158 158 case GE_ILLEGALOP: … … 178 178 break; 179 179 } 180 180 181 181 fault_if_from_uspace(istate, "General Exception (%s).", desc); 182 182 panic_badtrap(istate, n, "General Exception (%s).", desc); … … 209 209 istate->cr_ipsr.ri++; 210 210 } 211 211 212 212 interrupts_enable(); 213 213 ret = syscall_handler(istate->in0, istate->in1, istate->in2, … … 236 236 { 237 237 cr_ivr_t ivr; 238 238 239 239 ivr.value = ivr_read(); 240 240 srlz_d(); 241 241 242 242 irq_t *irq; 243 243 244 244 switch (ivr.vector) { 245 245 case INTERRUPT_SPURIOUS: … … 248 248 #endif 249 249 break; 250 250 251 251 #ifdef CONFIG_SMP 252 252 case VECTOR_TLB_SHOOTDOWN_IPI: … … 255 255 break; 256 256 #endif 257 257 258 258 case INTERRUPT_TIMER: 259 259 irq = irq_dispatch_and_lock(ivr.vector); -
kernel/arch/ia64/src/ivt.S
r3061bc1 ra35b458 57 57 mov r19 = cr.ipsr 58 58 mov r20 = cr.isr ;; 59 59 60 60 /* 2. Move IIP to IIPA. */ 61 61 mov cr.iipa = r18 62 62 63 63 /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */ 64 64 shl r17 = r17, 43 ;; /* shift bit 20 to bit 63 */ … … 66 66 add r18 = r18, r17 ;; 67 67 mov cr.iip = r18 68 68 69 69 /* 4. Set IPSR.ri to 0. */ 70 70 dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;; 71 71 mov cr.ipsr = r19 72 72 73 73 /* 5. Check whether IPSR.tb or IPSR.ss is set. */ 74 74 … … 76 76 * Implement this when Taken Branch and Single Step traps can occur. 77 77 */ 78 78 79 79 /* 6. Restore predicates and return from interruption. */ 80 80 mov pr = r16 ;; … … 104 104 SYMBOL(heavyweight_handler) 105 105 /* 1. copy interrupt registers into bank 0 */ 106 106 107 107 /* 108 108 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. 109 109 */ 110 110 111 111 /* Set up FPU as in interrupted context. */ 112 112 mov r24 = psr … … 126 126 mov r27 = cr.isr 127 127 mov r28 = cr.ifa 128 128 129 129 /* 2. preserve predicate register into bank 0 */ 130 130 mov r29 = pr ;; 131 131 132 132 /* 3. switch to kernel memory stack */ 133 133 mov r30 = cr.ipsr … … 149 149 */ 150 150 (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; 151 151 152 152 /* 153 153 * Now, p4 is true iff the stack needs to be switched to kernel stack. … … 155 155 mov r30 = r12 156 156 (p4) mov r12 = R_KSTACK ;; 157 157 158 158 add r12 = -STACK_FRAME_SIZE, r12 ;; 159 159 add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_IN6, r12 … … 166 166 */ 167 167 cmp.eq p6, p5 = EXC_BREAK_INSTRUCTION, R_VECTOR ;; 168 168 169 169 /* 170 170 * From now on, if this is break_instruction handler, p6 is true and p5 … … 181 181 (p6) st8 [r31] = r32, -STACK_ITEM_SIZE ;; /* save in0 */ 182 182 (p5) add r31 = -(7 * STACK_ITEM_SIZE), r31 ;; 183 183 184 184 st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save old stack pointer */ 185 185 186 186 st8 [r31] = r29, -STACK_ITEM_SIZE ;; /* save predicate registers */ 187 187 … … 197 197 cover 198 198 mov r26 = cr.ifs 199 199 200 200 st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save ar.rsc */ 201 201 st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save ar.pfs */ 202 202 st8 [r31] = r26, -STACK_ITEM_SIZE /* save ar.ifs */ 203 203 204 204 and r24 = ~(RSC_PL_MASK), r24 ;; 205 205 and r30 = ~(RSC_MODE_MASK), r24 ;; 206 206 mov ar.rsc = r30 ;; /* update RSE state */ 207 207 208 208 mov r27 = ar.rnat 209 209 mov r28 = ar.bspstore ;; 210 210 211 211 /* 212 212 * Inspect BSPSTORE to figure out whether it is necessary to switch to … … 215 215 (p1) shr.u r30 = r28, VRN_SHIFT ;; 216 216 (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; 217 217 218 218 /* 219 219 * If BSPSTORE needs to be switched, p1 is false and p2 is true. … … 222 222 (p2) mov r30 = R_KSTACK_BSP ;; 223 223 (p2) mov ar.bspstore = r30 ;; 224 224 225 225 mov r29 = ar.bsp 226 226 227 227 st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save ar.rnat */ 228 228 st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save new value written to ar.bspstore */ 229 229 st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save ar.bspstore */ 230 230 st8 [r31] = r29, -STACK_ITEM_SIZE /* save ar.bsp */ 231 231 232 232 mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ 233 233 234 234 /* steps 6 - 15 are done by heavyweight_handler_inner() */ 235 235 mov R_RET = b0 /* save b0 belonging to interrupted context */ … … 292 292 ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load predicate registers */ 293 293 mov pr = r29 294 294 295 295 /* 19. return from interruption */ 296 296 ld8 r12 = [r31] /* load stack pointer */ … … 303 303 */ 304 304 alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; 305 305 306 306 /* bank 0 is going to be shadowed, copy essential data from there */ 307 307 mov loc1 = R_RET /* b0 belonging to interrupted context */ 308 308 mov loc2 = R_HANDLER 309 309 mov out0 = R_VECTOR 310 310 311 311 add out1 = STACK_SCRATCH_AREA_SIZE, r12 312 312 … … 315 315 bsw.1 ;; 316 316 srlz.d 317 317 318 318 /* 7. preserve branch and application registers */ 319 319 mov loc3 = ar.unat … … 323 323 mov loc7 = ar.csd 324 324 mov loc8 = ar.ssd 325 325 326 326 mov loc9 = b0 327 327 mov loc10 = b1 … … 332 332 mov loc15 = b6 333 333 mov loc16 = b7 334 334 335 335 /* 8. preserve general and floating-point registers */ 336 336 mov loc17 = r1 … … 374 374 add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12 375 375 add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;; 376 376 377 377 stf.spill [r26] = f2, 8 * FLOAT_ITEM_SIZE 378 378 stf.spill [r27] = f3, 8 * FLOAT_ITEM_SIZE … … 410 410 411 411 mov loc47 = ar.fpsr /* preserve floating point status register */ 412 412 413 413 /* 9. skipped (will not enable interrupts) */ 414 414 /* … … 420 420 /* 10. call handler */ 421 421 movl r1 = __gp 422 422 423 423 mov b1 = loc2 424 424 br.call.sptk.many b0 = b1 … … 426 426 /* 11. return from handler */ 427 427 0: 428 428 429 429 /* 12. skipped (will not disable interrupts) */ 430 430 /* … … 477 477 ldf.fill f30 = [r30] 478 478 ldf.fill f31 = [r31] ;; 479 479 480 480 mov r1 = loc17 481 481 mov r2 = loc18 … … 511 511 512 512 mov ar.fpsr = loc47 /* restore floating point status register */ 513 513 514 514 /* 14. restore branch and application registers */ 515 515 mov ar.unat = loc3 … … 519 519 mov ar.csd = loc7 520 520 mov ar.ssd = loc8 521 521 522 522 mov b0 = loc9 523 523 mov b1 = loc10 … … 528 528 mov b6 = loc15 529 529 mov b7 = loc16 530 530 531 531 /* 15. disable PSR.ic and switch to bank 0 */ 532 532 rsm PSR_IC_MASK … … 578 578 HEAVYWEIGHT_HANDLER 0x5e 579 579 HEAVYWEIGHT_HANDLER 0x5f 580 580 581 581 HEAVYWEIGHT_HANDLER 0x60 582 582 HEAVYWEIGHT_HANDLER 0x61 -
kernel/arch/ia64/src/mm/as.c
r3061bc1 ra35b458 58 58 region_register_t rr; 59 59 int i; 60 60 61 61 assert(as->asid != ASID_INVALID); 62 62 63 63 /* 64 64 * Load respective ASID (7 consecutive RIDs) to … … 68 68 if (i == VRN_KERNEL) 69 69 continue; 70 70 71 71 rr.word = rr_read(i); 72 72 rr.map.ve = false; /* disable VHPT walker */ -
kernel/arch/ia64/src/mm/frame.c
r3061bc1 ra35b458 92 92 if (config.cpu_active > 1) 93 93 return; 94 94 95 95 frame_common_arch_init(true); 96 96 97 97 /* 98 98 * Blacklist ROM regions. … … 112 112 if (config.cpu_active > 1) 113 113 return; 114 114 115 115 frame_common_arch_init(false); 116 116 } -
kernel/arch/ia64/src/mm/page.c
r3061bc1 ra35b458 124 124 vrn = page >> VRN_SHIFT; 125 125 rid = ASID2RID(asid, vrn); 126 126 127 127 rr_save.word = rr_read(vrn); 128 128 if (rr_save.map.rid == rid) { … … 133 133 return v; 134 134 } 135 135 136 136 /* 137 137 * The RID must be written to some region register. … … 171 171 vrn = page >> VRN_SHIFT; 172 172 rid = ASID2RID(asid, vrn); 173 173 174 174 rr_save.word = rr_read(vrn); 175 175 if (rr_save.map.rid == rid) { … … 179 179 return ttag(page) == v->present.tag.tag_word; 180 180 } 181 181 182 182 /* 183 183 * The RID must be written to some region register. … … 218 218 vrn = page >> VRN_SHIFT; 219 219 rid = ASID2RID(asid, vrn); 220 220 221 221 /* 222 222 * Compute ttag. … … 231 231 srlz_i(); 232 232 srlz_d(); 233 233 234 234 /* 235 235 * Clear the entry. … … 239 239 v->word[2] = 0; 240 240 v->word[3] = 0; 241 241 242 242 v->present.p = true; 243 243 v->present.ma = (flags & PAGE_CACHEABLE) ? -
kernel/arch/ia64/src/mm/tlb.c
r3061bc1 ra35b458 61 61 uintptr_t adr; 62 62 uint32_t count1, count2, stride1, stride2; 63 63 64 64 unsigned int i, j; 65 65 66 66 adr = PAL_PTCE_INFO_BASE(); 67 67 count1 = PAL_PTCE_INFO_COUNT1(); … … 69 69 stride1 = PAL_PTCE_INFO_STRIDE1(); 70 70 stride2 = PAL_PTCE_INFO_STRIDE2(); 71 71 72 72 ipl = interrupts_disable(); 73 73 74 74 for (i = 0; i < count1; i++) { 75 75 for (j = 0; j < count2; j++) { … … 82 82 adr += stride1; 83 83 } 84 84 85 85 interrupts_restore(ipl); 86 86 87 87 srlz_d(); 88 88 srlz_i(); 89 89 90 90 #ifdef CONFIG_VHPT 91 91 vhpt_invalidate_all(); … … 110 110 int b = 0; 111 111 int c = cnt; 112 112 113 113 uintptr_t va; 114 114 va = page; 115 115 116 116 rr.word = rr_read(VA2VRN(page)); 117 117 if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) { … … 121 121 */ 122 122 region_register_t rr0; 123 123 124 124 rr0 = rr; 125 125 rr0.map.rid = ASID2RID(asid, VA2VRN(page)); … … 128 128 srlz_i(); 129 129 } 130 130 131 131 while (c >>= 1) 132 132 b++; 133 133 b >>= 1; 134 134 uint64_t ps; 135 135 136 136 switch (b) { 137 137 case 0: /* cnt 1 - 3 */ … … 172 172 break; 173 173 } 174 174 175 175 for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps)) 176 176 asm volatile ( … … 179 179 [ps] "r" (ps << 2) 180 180 ); 181 181 182 182 srlz_d(); 183 183 srlz_i(); 184 184 185 185 if (restore_rr) { 186 186 rr_write(VA2VRN(page), rr.word); … … 229 229 region_register_t rr; 230 230 bool restore_rr = false; 231 231 232 232 rr.word = rr_read(VA2VRN(va)); 233 233 if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { … … 237 237 */ 238 238 region_register_t rr0; 239 239 240 240 rr0 = rr; 241 241 rr0.map.rid = ASID2RID(asid, VA2VRN(va)); … … 244 244 srlz_i(); 245 245 } 246 246 247 247 asm volatile ( 248 248 "mov r8 = psr ;;\n" … … 264 264 : "p6", "p7", "r8" 265 265 ); 266 266 267 267 if (restore_rr) { 268 268 rr_write(VA2VRN(va), rr.word); … … 316 316 region_register_t rr; 317 317 bool restore_rr = false; 318 318 319 319 rr.word = rr_read(VA2VRN(va)); 320 320 if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { … … 324 324 */ 325 325 region_register_t rr0; 326 326 327 327 rr0 = rr; 328 328 rr0.map.rid = ASID2RID(asid, VA2VRN(va)); … … 331 331 srlz_i(); 332 332 } 333 333 334 334 asm volatile ( 335 335 "mov r8 = psr ;;\n" … … 352 352 : "p6", "p7", "r8" 353 353 ); 354 354 355 355 if (restore_rr) { 356 356 rr_write(VA2VRN(va), rr.word); … … 373 373 { 374 374 tlb_entry_t entry; 375 375 376 376 entry.word[0] = 0; 377 377 entry.word[1] = 0; 378 378 379 379 entry.p = true; /* present */ 380 380 entry.ma = MA_WRITEBACK; … … 385 385 entry.ppn = frame >> PPN_SHIFT; 386 386 entry.ps = PAGE_WIDTH; 387 387 388 388 if (dtr) 389 389 dtr_mapping_insert(page, ASID_KERNEL, entry, tr); … … 418 418 { 419 419 tlb_entry_t entry; 420 420 421 421 entry.word[0] = 0; 422 422 entry.word[1] = 0; 423 423 424 424 entry.p = t->p; 425 425 entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; … … 430 430 entry.ppn = t->frame >> PPN_SHIFT; 431 431 entry.ps = PAGE_WIDTH; 432 432 433 433 dtc_mapping_insert(t->page, t->as->asid, entry); 434 434 435 435 #ifdef CONFIG_VHPT 436 436 vhpt_mapping_insert(t->page, t->as->asid, entry); … … 446 446 { 447 447 tlb_entry_t entry; 448 448 449 449 entry.word[0] = 0; 450 450 entry.word[1] = 0; 451 451 452 452 assert(t->x); 453 453 454 454 entry.p = t->p; 455 455 entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; … … 459 459 entry.ppn = t->frame >> PPN_SHIFT; 460 460 entry.ps = PAGE_WIDTH; 461 461 462 462 itc_mapping_insert(t->page, t->as->asid, entry); 463 463 464 464 #ifdef CONFIG_VHPT 465 465 vhpt_mapping_insert(t->page, t->as->asid, entry); … … 486 486 uintptr_t va; 487 487 pte_t t; 488 488 489 489 va = istate->cr_ifa; /* faulting address */ 490 490 491 491 assert(!is_kernel_fault(va)); 492 492 … … 532 532 uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >> 533 533 LEGACYIO_SINGLE_PAGE_WIDTH; 534 534 535 535 if (is_io_page_accessible(io_page)) { 536 536 uint64_t page, frame; 537 537 538 538 page = LEGACYIO_USER_BASE + 539 539 (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; 540 540 frame = LEGACYIO_PHYS_BASE + 541 541 (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; 542 542 543 543 tlb_entry_t entry; 544 544 545 545 entry.word[0] = 0; 546 546 entry.word[1] = 0; 547 547 548 548 entry.p = true; /* present */ 549 549 entry.ma = MA_UNCACHEABLE; … … 554 554 entry.ppn = frame >> PPN_SHIFT; 555 555 entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH; 556 556 557 557 dtc_mapping_insert(page, TASK->as->asid, entry); 558 558 return 1; … … 563 563 } 564 564 } 565 565 566 566 return 0; 567 567 } … … 586 586 return; 587 587 } 588 588 589 589 uintptr_t va = istate->cr_ifa; /* faulting address */ 590 590 as_t *as = AS; 591 591 592 592 if (is_kernel_fault(va)) { 593 593 if (va < end_of_identity) { … … 601 601 } 602 602 } 603 604 603 604 605 605 pte_t t; 606 606 bool found = page_mapping_find(as, va, true, &t); … … 616 616 if (try_memmap_io_insertion(va, istate)) 617 617 return; 618 618 619 619 /* 620 620 * Forward the page fault to the address space page fault … … 649 649 pte_t t; 650 650 as_t *as = AS; 651 651 652 652 va = istate->cr_ifa; /* faulting address */ 653 653 654 654 if (is_kernel_fault(va)) 655 655 as = AS_KERNEL; … … 683 683 uintptr_t va; 684 684 pte_t t; 685 685 686 686 va = istate->cr_ifa; /* faulting address */ 687 687 688 688 assert(!is_kernel_fault(va)); 689 689 690 690 bool found = page_mapping_find(AS, va, true, &t); 691 691 … … 717 717 pte_t t; 718 718 as_t *as = AS; 719 719 720 720 va = istate->cr_ifa; /* faulting address */ 721 721 722 722 if (is_kernel_fault(va)) 723 723 as = AS_KERNEL; … … 755 755 uintptr_t va; 756 756 pte_t t; 757 757 758 758 va = istate->cr_ifa; /* faulting address */ 759 759 760 760 assert(!is_kernel_fault(va)); 761 761 762 762 /* 763 763 * Assume a write to a read-only page. … … 782 782 uintptr_t va; 783 783 pte_t t; 784 784 785 785 va = istate->cr_ifa; /* faulting address */ 786 786 787 787 assert(!is_kernel_fault(va)); 788 788 … … 790 790 791 791 assert(found); 792 792 793 793 if (t.p) { 794 794 /* -
kernel/arch/ia64/src/mm/vhpt.c
r3061bc1 ra35b458 46 46 if (!vhpt_frame) 47 47 panic("Kernel configured with VHPT but no memory for table."); 48 48 49 49 vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame); 50 50 vhpt_invalidate_all(); … … 59 59 rid_t rid; 60 60 uint64_t tag; 61 61 62 62 vhpt_entry_t *ventry; 63 63 64 64 vrn = va >> VRN_SHIFT; 65 65 rid = ASID2RID(asid, vrn); 66 66 67 67 rr_save.word = rr_read(vrn); 68 68 rr.word = rr_save.word; … … 70 70 rr_write(vrn, rr.word); 71 71 srlz_i(); 72 72 73 73 ventry = (vhpt_entry_t *) thash(va); 74 74 tag = ttag(va); … … 76 76 srlz_i(); 77 77 srlz_d(); 78 78 79 79 ventry->word[0] = entry.word[0]; 80 80 ventry->word[1] = entry.word[1]; -
kernel/arch/ia64/src/proc/scheduler.c
r3061bc1 ra35b458 54 54 { 55 55 uintptr_t base; 56 56 57 57 base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); 58 58 … … 63 63 * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it. 64 64 */ 65 65 66 66 /* purge DTR[TR_STACK1] and DTR[TR_STACK2] */ 67 67 dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1); 68 68 69 69 /* insert DTR[TR_STACK1] and DTR[TR_STACK2] */ 70 70 dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, … … 74 74 DTR_KSTACK2); 75 75 } 76 76 77 77 /* 78 78 * Record address of kernel backing store to bank 0 r22. -
kernel/arch/ia64/src/start.S
r3061bc1 ra35b458 54 54 SYMBOL(kernel_image_start) 55 55 .auto 56 56 57 57 mov psr.l = r0 58 58 srlz.i 59 59 srlz.d 60 60 61 61 # Fill TR.i and TR.d using Region Register #VRN_KERNEL 62 62 63 63 movl r8 = (VRN_KERNEL << VRN_SHIFT) 64 64 mov r9 = rr[r8] 65 65 66 66 movl r10 = (RR_MASK) 67 67 and r9 = r10, r9 68 68 movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) 69 69 or r9 = r10, r9 70 70 71 71 mov rr[r8] = r9 72 72 73 73 movl r8 = (VRN_KERNEL << VRN_SHIFT) 74 74 mov cr.ifa = r8 75 75 76 76 mov r11 = cr.itir 77 77 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT) 78 78 or r10 = r10, r11 79 79 mov cr.itir = r10 80 80 81 81 movl r10 = (KERNEL_TRANSLATION_I) 82 82 itr.i itr[r0] = r10 83 83 movl r10 = (KERNEL_TRANSLATION_D) 84 84 itr.d dtr[r0] = r10 85 85 86 86 # Initialize DCR 87 87 88 88 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK) 89 89 mov r9 = cr.dcr 90 90 or r10 = r10, r9 91 91 mov cr.dcr = r10 92 92 93 93 # Initialize PSR 94 94 95 95 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ 96 96 mov r9 = psr 97 97 98 98 or r10 = r10, r9 99 99 mov cr.ipsr = r10 … … 103 103 srlz.d 104 104 srlz.i 105 105 106 106 .explicit 107 107 108 108 /* 109 109 * Return From Interrupt is the only way to … … 113 113 114 114 paging_start: 115 115 116 116 /* 117 117 * Now we are paging. … … 126 126 srlz.d ;; 127 127 128 128 129 129 # Switch to register bank 1 130 130 bsw.1 131 131 132 132 # Initialize register stack 133 133 mov ar.rsc = r0 … … 135 135 mov ar.bspstore = r8 136 136 loadrs 137 137 138 138 # 139 139 # Initialize memory stack to some sane value and allocate a scratch area … … 142 142 movl sp = stack0 ;; 143 143 add sp = -16, sp 144 144 145 145 # Initialize gp (Global Pointer) register 146 146 movl gp = __gp 147 147 148 148 # 149 149 # Initialize bootinfo on BSP. … … 153 153 addl r21 = @gprel(bootinfo), gp ;; 154 154 st8 [r21] = r20 155 155 156 156 ssm (1 << 19) ;; /* Disable f32 - f127 */ 157 157 srlz.i 158 158 srlz.d ;; 159 159 160 160 br.call.sptk.many b0 = ia64_pre_main 161 161 0:
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