Changes in kernel/arch/amd64/src/pm.c [44a7ee5:a35b458] in mainline

File:

• kernel/arch/amd64/src/pm.c (modified) (5 diffs)

kernel/arch/amd64/src/pm.c

@@ -130 +130 @@
 {
         tss_descriptor_t *td = (tss_descriptor_t *) d;
-        
+
         td->base_0_15 = base & 0xffffU;
         td->base_16_23 = ((base) >> 16) & 0xffU;
@@ -140 +140 @@
 {
         tss_descriptor_t *td = (tss_descriptor_t *) d;
-        
+
         td->limit_0_15 = limit & 0xffffU;
         td->limit_16_19 = (limit >> 16) & 0x0fU;
@@ -167 +167 @@
         idescriptor_t *d;
         unsigned int i;
-        
+
         for (i = 0; i < IDT_ITEMS; i++) {
                 d = &idt[i];
-                
+
                 d->unused = 0;
                 d->selector = GDT_SELECTOR(KTEXT_DES);
-                
+
                 d->present = 1;
                 d->type = AR_INTERRUPT;  /* masking interrupt */
         }
-        
+
         d = &idt[0];
         idt_setoffset(d++, (uintptr_t) &int_0);
@@ -252 +252 @@
         descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
         tss_descriptor_t *tss_desc;
-        
+
         /*
          * Each CPU has its private GDT and TSS.
          * All CPUs share one IDT.
          */
-        
+
         if (config.cpu_active == 1) {
                 idt_init();
@@ -270 +270 @@
                  * ahead of page_init */
                 write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
-                
+
                 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
                 if (!tss_p)
                         panic("Cannot allocate TSS.");
         }
-        
+
         tss_initialize(tss_p);
-        
+
         tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
         tss_desc->present = 1;
         tss_desc->type = AR_TSS;
         tss_desc->dpl = PL_KERNEL;
-        
+
         gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
         gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
-        
+
         gdtr_load(&gdtr);
         idtr_load(&idtr);