Changes in boot/arch/sparc64/src/asm.S [a52e2f4:a35b458] in mainline
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boot/arch/sparc64/src/asm.S
ra52e2f4 ra35b458 65 65 1: 66 66 ! Disable interrupts and disable address masking. 67 67 68 68 wrpr %g0, PSTATE_PRIV_BIT, %pstate 69 69 70 70 wrpr %g0, NWINDOWS - 2, %cansave ! Set maximum saveable windows 71 71 wrpr %g0, 0, %canrestore ! Get rid of windows we will never need again 72 72 wrpr %g0, 0, %otherwin ! Make sure the window state is consistent 73 73 wrpr %g0, NWINDOWS - 1, %cleanwin ! Prevent needless clean_window traps for kernel 74 74 75 75 set initial_stack, %sp 76 76 add %sp, -STACK_BIAS, %sp 77 77 78 78 set ofw_cif, %l0 79 79 80 80 ! Initialize OpenFirmware 81 81 82 82 call ofw_init 83 83 stx %o4, [%l0] 84 84 85 85 ba %xcc, bootstrap 86 86 nop … … 105 105 * 3. Flush instruction pipeline. 106 106 */ 107 107 108 108 /* 109 109 * US3 processors have a write-invalidate cache, so explicitly … … 115 115 be %xcc, 1f 116 116 nop 117 117 118 118 0: 119 119 call icache_flush 120 120 nop 121 121 122 122 1: 123 123 membar #StoreStore 124 124 125 125 /* 126 126 * Flush the instruction pipeline. 127 127 */ 128 128 flush %i7 129 129 130 130 ! Jump to kernel 131 131 jmp %o3 … … 138 138 set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 139 139 stxa %g0, [%g1] ASI_ICACHE_TAG 140 140 141 141 0: 142 142 membar #Sync 143 143 subcc %g1, ICACHE_LINE_SIZE, %g1 144 144 bnz,pt %xcc, 0b 145 145 146 146 stxa %g0, [%g1] ASI_ICACHE_TAG 147 147 membar #Sync 148 148 retl 149 149 150 150 ! SF Erratum #51 151 151 152 152 nop 153 153 #else … … 161 161 set ofw_cif, %l0 162 162 ldx [%l0], %l0 163 163 164 164 rdpr %pstate, %l1 165 165 and %l1, ~PSTATE_AM_BIT, %l2 166 166 wrpr %l2, 0, %pstate 167 167 168 168 jmpl %l0, %o7 169 169 mov %i0, %o0 170 170 171 171 wrpr %l1, 0, %pstate 172 172 173 173 ret 174 174 restore %o0, 0, %o0
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