Index: arch/ia32/include/smp/mps.h
===================================================================
--- arch/ia32/include/smp/mps.h	(revision 6b7c36f80b96691f347bd14dd1268ac4f9689f77)
+++ arch/ia32/include/smp/mps.h	(revision a26ddd11445ebfd4a188b1e7aba9091fb10326d5)
@@ -34,4 +34,5 @@
 #include <synch/waitq.h>
 #include <config.h>
+#include <arch/smp/smp.h>
 
 #define CT_EXT_ENTRY_TYPE		0
@@ -118,4 +119,6 @@
 extern waitq_t kmp_completion_wq;
 
+extern struct smp_config_operations mps_config_operations;
+
 extern int mps_irq_to_pin(int irq);
 
Index: arch/ia32/include/smp/smp.h
===================================================================
--- arch/ia32/include/smp/smp.h	(revision a26ddd11445ebfd4a188b1e7aba9091fb10326d5)
+++ arch/ia32/include/smp/smp.h	(revision a26ddd11445ebfd4a188b1e7aba9091fb10326d5)
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ia32_SMP_H__
+#define __ia32_SMP_H__
+
+#include <arch/types.h>
+#include <typedefs.h>
+
+struct smp_config_operations {
+	count_t (* cpu_count)(void);
+	bool (* cpu_enabled)(index_t i);
+	bool (*cpu_bootstrap)(index_t i);
+	__u8 (*cpu_apic_id)(index_t i);
+};
+
+#endif
Index: arch/ia32/src/smp/mps.c
===================================================================
--- arch/ia32/src/smp/mps.c	(revision 6b7c36f80b96691f347bd14dd1268ac4f9689f77)
+++ arch/ia32/src/smp/mps.c	(revision a26ddd11445ebfd4a188b1e7aba9091fb10326d5)
@@ -29,24 +29,17 @@
 #ifdef __SMP__
 
-#include <arch/pm.h>
 #include <config.h>
 #include <print.h>
-#include <panic.h>
+#include <debug.h>
 #include <arch/smp/mps.h>
-#include <arch/smp/ap.h>
 #include <arch/smp/apic.h>
+#include <arch/smp/smp.h>
 #include <func.h>
 #include <arch/types.h>
 #include <typedefs.h>
-#include <synch/waitq.h>
-#include <time/delay.h>
-#include <mm/heap.h>
 #include <mm/page.h>
-#include <mm/frame.h>
 #include <cpu.h>
-#include <arch/i8259.h>
 #include <arch/asm.h>
 #include <arch/bios/bios.h>
-#include <arch/acpi/madt.h>
 
 /*
@@ -88,4 +81,44 @@
 waitq_t ap_completion_wq;
 waitq_t kmp_completion_wq;
+
+
+/*
+ * Implementation of IA-32 SMP configuration interface.
+ */
+static count_t get_cpu_count(void);
+static bool is_cpu_enabled(index_t i);
+static bool is_bsp(index_t i);
+static __u8 get_cpu_apic_id(index_t i);
+
+struct smp_config_operations mps_config_operations = {
+	.cpu_count = get_cpu_count,
+	.cpu_enabled = is_cpu_enabled,
+	.cpu_bootstrap = is_bsp,
+	.cpu_apic_id = get_cpu_apic_id
+};
+
+count_t get_cpu_count(void)
+{
+	return processor_entry_cnt;
+}
+
+bool is_cpu_enabled(index_t i)
+{
+	ASSERT(i < processor_entry_cnt);
+	return processor_entries[i].cpu_flags & 0x1;
+}
+
+bool is_bsp(index_t i)
+{
+	ASSERT(i < processor_entry_cnt);
+	return processor_entries[i].cpu_flags & 0x2;
+}
+
+__u8 get_cpu_apic_id(index_t i)
+{
+	ASSERT(i < processor_entry_cnt);
+	return processor_entries[i].l_apic_id;
+}
+
 
 /*
@@ -393,99 +426,4 @@
 }
 
-
-/*
- * Kernel thread for bringing up application processors. It becomes clear
- * that we need an arrangement like this (AP's being initialized by a kernel
- * thread), for a thread has its dedicated stack. (The stack used during the
- * BSP initialization (prior the very first call to scheduler()) will be used
- * as an initialization stack for each AP.)
- */
-void kmp(void *arg)
-{
-	struct __processor_entry *pr;
-	__address src, dst;
-	int i;
-
-	waitq_initialize(&ap_completion_wq);
-
-	/*
-	 * Processor entries immediately follow the configuration table header.
-	 */
-	pr = processor_entries;
-
-	/*
-	 * We need to access data in frame 0.
-	 * We boldly make use of kernel address space mapping.
-	 */
-
-	/*
-	 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
-	 */
-	*((__u16 *) (PA2KA(0x467+0))) =  ((__address) ap_boot) >> 4;	/* segment */
-	*((__u16 *) (PA2KA(0x467+2))) =  0;				/* offset */
-	
-	/*
-	 * Save 0xa to address 0xf of the CMOS RAM.
-	 * BIOS will not do the POST after the INIT signal.
-	 */
-	outb(0x70,0xf);
-	outb(0x71,0xa);
-
-	cpu_priority_high();
-
-	pic_disable_irqs(0xffff);
-	apic_init();
-
-	for (i = 0; i < processor_entry_cnt; i++) {
-		struct descriptor *gdt_new;
-	
-		/*
-		 * Skip processors marked unusable.
-		 */
-		if (pr[i].cpu_flags & (1<<0) == 0)
-			continue;
-
-		/*
-		 * The bootstrap processor is already up.
-		 */
-		if (pr[i].cpu_flags & (1<<1))
-			continue;
-
-		if (pr[i].l_apic_id == l_apic_id()) {
-			printf("%L: bad processor entry #%d, will not send IPI to myself\n", &pr[i], i);
-			continue;
-		}
-		
-		/*
-		 * Prepare new GDT for CPU in question.
-		 */
-		if (!(gdt_new = (struct descriptor *) malloc(GDT_ITEMS*sizeof(struct descriptor))))
-			panic("couldn't allocate memory for GDT\n");
-
-		memcopy(gdt, gdt_new, GDT_ITEMS*sizeof(struct descriptor));
-		memsetb(&gdt_new[TSS_DES], sizeof(struct descriptor), 0);
-		gdtr.base = KA2PA((__address) gdt_new);
-
-		if (l_apic_send_init_ipi(pr[i].l_apic_id)) {
-			/*
-		         * There may be just one AP being initialized at
-			 * the time. After it comes completely up, it is
-			 * supposed to wake us up.
-		         */
-			waitq_sleep(&ap_completion_wq);
-			cpu_priority_high();
-		}
-		else {
-			printf("INIT IPI for l_apic%d failed\n", pr[i].l_apic_id);
-		}
-	}
-
-	/*
-	 * Wakeup the kinit thread so that
-	 * system initialization can go on.
-	 */
-	waitq_wakeup(&kmp_completion_wq, WAKEUP_FIRST);
-}
-
 int mps_irq_to_pin(int irq)
 {
Index: arch/ia32/src/smp/smp.c
===================================================================
--- arch/ia32/src/smp/smp.c	(revision 6b7c36f80b96691f347bd14dd1268ac4f9689f77)
+++ arch/ia32/src/smp/smp.c	(revision a26ddd11445ebfd4a188b1e7aba9091fb10326d5)
@@ -28,10 +28,23 @@
 
 #include <smp/smp.h>
+#include <arch/smp/smp.h>
+#include <arch/smp/mps.h>
+#include <arch/smp/ap.h>
 #include <arch/acpi/acpi.h>
 #include <arch/acpi/madt.h>
-#include <arch/smp/mps.h>
 #include <config.h>
+#include <synch/waitq.h>
+#include <arch/pm.h>
+#include <func.h>
+#include <panic.h>
+#include <debug.h>
+#include <arch/asm.h>
+#include <mm/frame.h>
+#include <mm/page.h>
+#include <mm/heap.h>
 
 #ifdef __SMP__
+
+static struct smp_config_operations *ops = NULL;
 
 void smp_init(void)
@@ -40,8 +53,99 @@
 		acpi_madt_parse();
 	}
-	if (config.cpu_count == 1)
+	if (config.cpu_count == 1) {
 		mps_init();
+		ops = &mps_config_operations;
+	}
 }
 
+/*
+ * Kernel thread for bringing up application processors. It becomes clear
+ * that we need an arrangement like this (AP's being initialized by a kernel
+ * thread), for a thread has its dedicated stack. (The stack used during the
+ * BSP initialization (prior the very first call to scheduler()) will be used
+ * as an initialization stack for each AP.)
+ */
+void kmp(void *arg)
+{
+	__address src, dst;
+	int i;
+
+	ASSERT(ops != NULL);
+
+	waitq_initialize(&ap_completion_wq);
+
+	/*
+	 * We need to access data in frame 0.
+	 * We boldly make use of kernel address space mapping.
+	 */
+
+	/*
+	 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
+	 */
+	*((__u16 *) (PA2KA(0x467+0))) =  ((__address) ap_boot) >> 4;	/* segment */
+	*((__u16 *) (PA2KA(0x467+2))) =  0;				/* offset */
+	
+	/*
+	 * Save 0xa to address 0xf of the CMOS RAM.
+	 * BIOS will not do the POST after the INIT signal.
+	 */
+	outb(0x70,0xf);
+	outb(0x71,0xa);
+
+	cpu_priority_high();
+
+	pic_disable_irqs(0xffff);
+	apic_init();
+
+	for (i = 0; i < ops->cpu_count(); i++) {
+		struct descriptor *gdt_new;
+	
+		/*
+		 * Skip processors marked unusable.
+		 */
+		if (!ops->cpu_enabled(i))
+			continue;
+
+		/*
+		 * The bootstrap processor is already up.
+		 */
+		if (ops->cpu_bootstrap(i))
+			continue;
+
+		if (ops->cpu_apic_id(i) == l_apic_id()) {
+			printf("kmp: bad processor entry #%d, will not send IPI to myself\n", i);
+			continue;
+		}
+		
+		/*
+		 * Prepare new GDT for CPU in question.
+		 */
+		if (!(gdt_new = (struct descriptor *) malloc(GDT_ITEMS*sizeof(struct descriptor))))
+			panic("couldn't allocate memory for GDT\n");
+
+		memcopy(gdt, gdt_new, GDT_ITEMS*sizeof(struct descriptor));
+		memsetb(&gdt_new[TSS_DES], sizeof(struct descriptor), 0);
+		gdtr.base = KA2PA((__address) gdt_new);
+
+		if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
+			/*
+		         * There may be just one AP being initialized at
+			 * the time. After it comes completely up, it is
+			 * supposed to wake us up.
+		         */
+			waitq_sleep(&ap_completion_wq);
+			cpu_priority_high();
+		}
+		else {
+			printf("INIT IPI for l_apic%d failed\n", ops->cpu_apic_id(i));
+		}
+	}
+
+	/*
+	 * Wakeup the kinit thread so that
+	 * system initialization can go on.
+	 */
+	waitq_wakeup(&kmp_completion_wq, WAKEUP_FIRST);
+}
 
 #endif /* __SMP__ */
