Index: kernel/arch/sparc64/src/asm.S
===================================================================
--- kernel/arch/sparc64/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/asm.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -47,12 +47,12 @@
 	add %o0, 7, %g1
 	mov 0, %g3
-	
+
 	0:
-	
+
 		brz,pn %o2, 2f
 		mov 0, %g2
-	
+
 	1:
-	
+
 		lduba [%g3 + %o1] ASI_AIUS, %g1
 		add %g2, 1, %g2
@@ -61,12 +61,12 @@
 		bne,pt %xcc, 1b
 		mov %g2, %g3
-	
+
 	2:
-	
+
 		jmp %o7 + 8  /* exit point */
 		mov %o3, %o0
-	
+
 	3:
-	
+
 		and %g1, -8, %g1
 		cmp %o0, %g1
@@ -76,7 +76,7 @@
 		brz,pn %g4, 5f
 		mov 0, %g5
-	
+
 	4:
-	
+
 		sllx %g3, 3, %g2
 		add %g5, 1, %g3
@@ -86,7 +86,7 @@
 		bne,pt %xcc, 4b
 		stx %g1, [%o0 + %g2]
-	
+
 	5:
-	
+
 		and %o2, 7, %o2
 		brz,pn %o2, 2b
@@ -96,7 +96,7 @@
 		add %g1, %o1, %g4
 		mov 0, %g3
-	
+
 	6:
-	
+
 		lduba [%g2 + %g4] ASI_AIUS, %g1
 		stb %g1, [%g2 + %o0]
@@ -105,5 +105,5 @@
 		bne,pt %xcc, 6b
 		mov %g2, %g3
-		
+
 		jmp %o7 + 8  /* exit point */
 		mov %o3, %o0
@@ -121,12 +121,12 @@
 	add %o0, 7, %g1
 	mov 0, %g3
-	
+
 	0:
-	
+
 		brz,pn %o2, 2f
 		mov 0, %g2
-	
+
 	1:
-	
+
 		ldub [%g3 + %o1], %g1
 		add %g2, 1, %g2
@@ -135,12 +135,12 @@
 		bne,pt %xcc, 1b
 		mov %g2, %g3
-	
+
 	2:
-	
+
 		jmp %o7 + 8  /* exit point */
 		mov %o3, %o0
-	
+
 	3:
-	
+
 		and %g1, -8, %g1
 		cmp %o0, %g1
@@ -150,7 +150,7 @@
 		brz,pn %g4, 5f
 		mov 0, %g5
-	
+
 	4:
-	
+
 		sllx %g3, 3, %g2
 		add %g5, 1, %g3
@@ -160,7 +160,7 @@
 		bne,pt %xcc, 4b
 		stxa %g1, [%o0 + %g2] ASI_AIUS
-	
+
 	5:
-	
+
 		and %o2, 7, %o2
 		brz,pn %o2, 2b
@@ -170,7 +170,7 @@
 		add %g1, %o1, %g4
 		mov 0, %g3
-	
+
 	6:
-	
+
 		ldub [%g2 + %g4], %g1
 		stba %g1, [%g2 + %o0] ASI_AIUS
@@ -179,5 +179,5 @@
 		bne,pt %xcc, 6b
 		mov %g2, %g3
-		
+
 		jmp	%o7 + 8  /* exit point */
 		mov	%o3, %o0
Index: kernel/arch/sparc64/src/console.c
===================================================================
--- kernel/arch/sparc64/src/console.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/console.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -69,5 +69,5 @@
 	if (!screen)
 		panic("Cannot find %s.", (char *) prop_scr->value);
-	
+
 	scr_init(screen);
 #endif
@@ -82,5 +82,5 @@
 	if (!keyboard)
 		panic("Cannot find %s.", (char *) prop_kbd->value);
-	
+
 	kbd_init(keyboard);
 #endif
@@ -95,12 +95,12 @@
 	ofw_tree_node_t *aliases;
 	ofw_tree_property_t *prop;
-	
+
 	aliases = ofw_tree_lookup("/aliases");
 	if (!aliases)
 		panic("Cannot find '/aliases'.");
-	
+
 	/* "def-cn" = "default console" */
 	prop = ofw_tree_getprop(aliases, "def-cn");
-	
+
 	if ((!prop) || (!prop->value))
 		standard_console_init(aliases);
Index: kernel/arch/sparc64/src/cpu/sun4u/cpu.c
===================================================================
--- kernel/arch/sparc64/src/cpu/sun4u/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/cpu/sun4u/cpu.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -59,5 +59,5 @@
 	if ((!prop) || (!prop->value))
 		prop = ofw_tree_getprop(node, "cpuid");
-	
+
 	if (prop && prop->value) {
 		mid = *((uint32_t *) prop->value);
@@ -69,5 +69,5 @@
 		}
 	}
-	
+
 	return -1;
 }
@@ -80,7 +80,7 @@
 	ofw_tree_node_t *node;
 	uint32_t clock_frequency = 0;
-	
+
 	CPU->arch.mid = read_mid();
-	
+
 	/*
 	 * Detect processor frequency.
@@ -109,5 +109,5 @@
 		}
 	}
-		
+
 	CPU->arch.clock_frequency = clock_frequency;
 	tick_init();
@@ -146,5 +146,5 @@
 		break;
 	}
-	
+
 	switch (CPU->arch.ver.impl) {
 	case IMPL_ULTRASPARCI:
Index: kernel/arch/sparc64/src/cpu/sun4v/cpu.c
===================================================================
--- kernel/arch/sparc64/src/cpu/sun4v/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/cpu/sun4v/cpu.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -71,5 +71,5 @@
 		}
 	}
-		
+
 	tick_init();
 
Index: kernel/arch/sparc64/src/debug/stacktrace.c
===================================================================
--- kernel/arch/sparc64/src/debug/stacktrace.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/debug/stacktrace.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -57,5 +57,5 @@
 {
 	uintptr_t kstack;
-	
+
 #if defined(SUN4U)
 	kstack = read_from_ag_g6();
Index: kernel/arch/sparc64/src/drivers/kbd.c
===================================================================
--- kernel/arch/sparc64/src/drivers/kbd.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/drivers/kbd.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -62,8 +62,8 @@
 {
 	const char *name = ofw_tree_node_name(node);
-	
+
 	if (str_cmp(name, "su") != 0)
 		return false;
-	
+
 	/*
 	 * Read 'interrupts' property.
@@ -75,7 +75,7 @@
 		return false;
 	}
-	
+
 	uint32_t interrupts = *((uint32_t *) prop->value);
-	
+
 	/*
 	 * Read 'reg' property.
@@ -87,7 +87,7 @@
 		return false;
 	}
-	
+
 	size_t size = ((ofw_ebus_reg_t *) prop->value)->size;
-	
+
 	uintptr_t pa = 0; // Prevent -Werror=maybe-uninitialized
 	if (!ofw_ebus_apply_ranges(node->parent,
@@ -97,5 +97,5 @@
 		return false;
 	}
-	
+
 	inr_t inr;
 	cir_t cir;
@@ -108,5 +108,5 @@
 		return false;
 	}
-	
+
 	/*
 	 * We need to pass aligned address to hw_map().
@@ -117,8 +117,8 @@
 	uintptr_t aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
 	size_t offset = pa - aligned_addr;
-	
+
 	ioport8_t *ns16550 = (ioport8_t *) (km_map(aligned_addr, offset + size,
 	    PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset);
-	
+
 	ns16550_instance_t *ns16550_instance = ns16550_init(ns16550, 0, inr, cir,
 	    cir_arg, NULL);
@@ -131,5 +131,5 @@
 		}
 	}
-	
+
 	/*
 	 * This is the necessary evil until the userspace drivers are
@@ -140,5 +140,5 @@
 	sysinfo_set_item_val("kbd.address.physical", NULL, pa);
 	sysinfo_set_item_val("kbd.type.ns16550", NULL, true);
-	
+
 	return true;
 }
Index: kernel/arch/sparc64/src/drivers/niagara.c
===================================================================
--- kernel/arch/sparc64/src/drivers/niagara.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/drivers/niagara.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -126,5 +126,5 @@
 	 * shared buffer to the console.
 	 */
-	
+
 	while (output_buffer.read_ptr != output_buffer.write_ptr) {
 		do_putchar(output_buffer.data[output_buffer.read_ptr]);
@@ -132,9 +132,9 @@
 		    ((output_buffer.read_ptr) + 1) % OUTPUT_BUFFER_SIZE;
 	}
-	
+
 	/*
 	 * Read character from keyboard.
 	 */
-	
+
 	uint64_t c;
 	if (__hypercall_fast_ret1(0, 0, 0, 0, 0, CONS_GETCHAR, &c) == HV_EOK) {
@@ -174,9 +174,9 @@
 	if (instance)
 		return;
-	
+
 	instance = malloc(sizeof(niagara_instance_t), FRAME_ATOMIC);
 	instance->thread = thread_create(kniagarapoll, NULL, TASK,
 	    THREAD_FLAG_UNCOUNTED, "kniagarapoll");
-	
+
 	if (!instance->thread) {
 		free(instance);
@@ -184,12 +184,12 @@
 		return;
 	}
-	
+
 	instance->srlnin = NULL;
-	
+
 	output_buffer.read_ptr = 0;
 	output_buffer.write_ptr = 0;
 	input_buffer.write_ptr = 0;
 	input_buffer.read_ptr = 0;
-	
+
 	/*
 	 * Set sysinfos and pareas so that the userspace counterpart of the
@@ -197,8 +197,8 @@
 	 * buffers.
 	 */
-	
+
 	sysinfo_set_item_val("fb", NULL, true);
 	sysinfo_set_item_val("fb.kind", NULL, 5);
-	
+
 	sysinfo_set_item_val("niagara.outbuf.address", NULL,
 	    KA2PA(&output_buffer));
@@ -207,5 +207,5 @@
 	sysinfo_set_item_val("niagara.outbuf.datasize", NULL,
 	    OUTPUT_BUFFER_SIZE);
-	
+
 	sysinfo_set_item_val("niagara.inbuf.address", NULL,
 	    KA2PA(&input_buffer));
@@ -214,5 +214,5 @@
 	sysinfo_set_item_val("niagara.inbuf.datasize", NULL,
 	   INPUT_BUFFER_SIZE);
-	
+
 	outbuf_parea.pbase = (uintptr_t) (KA2PA(&output_buffer));
 	outbuf_parea.frames = 1;
@@ -220,5 +220,5 @@
 	outbuf_parea.mapped = false;
 	ddi_parea_register(&outbuf_parea);
-	
+
 	inbuf_parea.pbase = (uintptr_t) (KA2PA(&input_buffer));
 	inbuf_parea.frames = 1;
@@ -226,5 +226,5 @@
 	inbuf_parea.mapped = false;
 	ddi_parea_register(&inbuf_parea);
-	
+
 	outdev_t *niagara_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
 	outdev_initialize("niagara_dev", niagara_dev, &niagara_ops);
@@ -238,5 +238,5 @@
 {
 	niagara_init();
-	
+
 	if (instance) {
 		srln_instance_t *srln_instance = srln_init();
@@ -244,10 +244,10 @@
 			indev_t *sink = stdin_wire();
 			indev_t *srln = srln_wire(srln_instance, sink);
-			
+
 			instance->srlnin = srln;
 			thread_ready(instance->thread);
 		}
 	}
-	
+
 	return instance;
 }
Index: kernel/arch/sparc64/src/drivers/pci.c
===================================================================
--- kernel/arch/sparc64/src/drivers/pci.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/drivers/pci.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -183,5 +183,5 @@
 	if (!prop || !prop->value)
 		return NULL;
-	
+
 	if (str_cmp(prop->value, "SUNW,sabre") == 0) {
 		/*
Index: kernel/arch/sparc64/src/drivers/scr.c
===================================================================
--- kernel/arch/sparc64/src/drivers/scr.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/drivers/scr.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -67,7 +67,7 @@
 	ofw_sbus_reg_t *sbus_reg;
 	const char *name;
-	
+
 	name = ofw_tree_node_name(node);
-	
+
 	if (str_cmp(name, "SUNW,m64B") == 0)
 		scr_type = SCR_ATYFB;
@@ -80,10 +80,10 @@
 	else if (str_cmp(name, "QEMU,VGA") == 0)
 		scr_type = SCR_QEMU_VGA;
-	
+
 	if (scr_type == SCR_UNKNOWN) {
 		log(LF_ARCH, LVL_ERROR, "Unknown screen device.");
 		return;
 	}
-	
+
 	uintptr_t fb_addr;
 	unsigned int fb_offset = 0;
@@ -121,7 +121,7 @@
 			return;
 		}
-	
+
 		pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
-		
+
 		if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
 			log(LF_ARCH, LVL_ERROR,
@@ -129,5 +129,5 @@
 			return;
 		}
-	
+
 		if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
 		    &fb_addr)) {
@@ -136,5 +136,5 @@
 			return;
 		}
-		
+
 		switch (fb_depth) {
 		case 8:
@@ -159,5 +159,5 @@
 			return;
 		}
-		
+
 		break;
 	case SCR_XVR:
@@ -167,7 +167,7 @@
 			return;
 		}
-	
+
 		pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
-		
+
 		if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
 			log(LF_ARCH, LVL_ERROR,
@@ -175,5 +175,5 @@
 			return;
 		}
-	
+
 		if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
 		    &fb_addr)) {
@@ -207,5 +207,5 @@
 			return;
 		}
-		
+
 		break;
 	case SCR_FFB:
@@ -231,5 +231,5 @@
 			return;
 		}
-		
+
 		sbus_reg = &((ofw_sbus_reg_t *) prop->value)[0];
 		if (!ofw_sbus_apply_ranges(node->parent, sbus_reg, &fb_addr)) {
@@ -238,5 +238,5 @@
 			return;
 		}
-	
+
 		break;
 
@@ -297,5 +297,5 @@
 		.visual = visual,
 	};
-	
+
 	outdev_t *fbdev = fb_init(&props);
 	if (fbdev)
Index: kernel/arch/sparc64/src/drivers/tick.c
===================================================================
--- kernel/arch/sparc64/src/drivers/tick.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/drivers/tick.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -89,10 +89,10 @@
 
 	softint.value = softint_read();
-	
+
 	/*
 	 * Make sure we are servicing interrupt_level_14
 	 */
 	assert(n == TT_INTERRUPT_LEVEL_14);
-	
+
 	/*
 	 * Make sure we are servicing TICK_INT.
@@ -106,5 +106,5 @@
 	clear.tick_int = 1;
 	clear_softint_write(clear.value);
-	
+
 	/*
 	 * Reprogram the compare register.
Index: kernel/arch/sparc64/src/fpu_context.c
===================================================================
--- kernel/arch/sparc64/src/fpu_context.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/fpu_context.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -67,5 +67,5 @@
 	 * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
 	 */
-	
+
 	asm volatile (
 		"std %%f32, %0\n"
@@ -90,5 +90,5 @@
 		  "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
 	);
-	
+
 	asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
 }
@@ -119,10 +119,10 @@
 		  "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
 	);
-	
+
 	/*
 	 * We need to split loading of the floating-point registers because
 	 * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
 	 */
-	
+
 	asm volatile (
 		"ldd %0, %%f32\n"
@@ -148,5 +148,5 @@
 		  "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
 	);
-	
+
 	asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
 }
@@ -155,5 +155,5 @@
 {
 	pstate_reg_t pstate;
-	
+
 	pstate.value = pstate_read();
 	pstate.pef = true;
@@ -164,5 +164,5 @@
 {
 	pstate_reg_t pstate;
-	
+
 	pstate.value = pstate_read();
 	pstate.pef = false;
Index: kernel/arch/sparc64/src/mm/sun4u/as.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/as.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4u/as.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -69,9 +69,9 @@
 	tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_base);
 	memsetb(tsb, TSB_SIZE, 0);
-	
+
 	as->arch.itsb = tsb;
 	as->arch.dtsb = tsb + ITSB_ENTRY_COUNT;
 #endif
-	
+
 	return EOK;
 }
@@ -81,5 +81,5 @@
 #ifdef CONFIG_TSB
 	frame_free(KA2PA((uintptr_t) as->arch.itsb), TSB_FRAMES);
-	
+
 	return TSB_FRAMES;
 #else
@@ -93,5 +93,5 @@
 	tsb_invalidate(as, 0, (size_t) -1);
 #endif
-	
+
 	return 0;
 }
@@ -107,5 +107,5 @@
 {
 	tlb_context_reg_t ctx;
-	
+
 	/*
 	 * Note that we don't and may not lock the address space. That's ok
@@ -115,5 +115,5 @@
 	 *
 	 */
-	
+
 	/*
 	 * Write ASID to secondary context register. The primary context
@@ -126,13 +126,13 @@
 	ctx.context = as->asid;
 	mmu_secondary_context_write(ctx.v);
-	
+
 #ifdef CONFIG_TSB
 	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-	
+
 	assert(as->arch.itsb);
 	assert(as->arch.dtsb);
-	
+
 	uintptr_t tsb = (uintptr_t) as->arch.itsb;
-	
+
 	if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
 		/*
@@ -145,5 +145,5 @@
 		dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
 	}
-	
+
 	/*
 	 * Setup TSB Base registers.
@@ -151,14 +151,14 @@
 	 */
 	tsb_base_reg_t tsb_base_reg;
-	
+
 	tsb_base_reg.value = 0;
 	tsb_base_reg.size = TSB_BASE_REG_SIZE;
 	tsb_base_reg.split = 0;
-	
+
 	tsb_base_reg.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
 	itsb_base_write(tsb_base_reg.value);
 	tsb_base_reg.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
 	dtsb_base_write(tsb_base_reg.value);
-	
+
 #if defined (US3)
 	/*
@@ -198,13 +198,13 @@
 	 *
 	 */
-	
+
 #ifdef CONFIG_TSB
 	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-	
+
 	assert(as->arch.itsb);
 	assert(as->arch.dtsb);
-	
+
 	uintptr_t tsb = (uintptr_t) as->arch.itsb;
-	
+
 	if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
 		/*
Index: kernel/arch/sparc64/src/mm/sun4u/frame.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4u/frame.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -48,5 +48,5 @@
 {
 	unsigned int i;
-	
+
 	for (i = 0; i < memmap.cnt; i++) {
 		uintptr_t base;
@@ -62,8 +62,8 @@
 		size = ALIGN_DOWN(memmap.zones[i].size -
 		    (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE);
-		
+
 		if (!frame_adjust_zone_bounds(low, &base, &size))
 			continue;
- 
+
 		pfn_t confdata;
 		pfn_t pfn = ADDR2PFN(base);
@@ -74,5 +74,5 @@
 			if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0))))
 				confdata = ADDR2PFN(KA2PA(PFN2ADDR(2)));
-			
+
 			zone_create(pfn, count, confdata,
 			    ZONE_AVAILABLE | ZONE_LOWMEM);
@@ -90,7 +90,7 @@
 	if (config.cpu_active > 1)
 		return;
-	
+
 	frame_common_arch_init(true);
-	
+
 	/*
 	 * On sparc64, physical memory can start on a non-zero address.
Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4u/tlb.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -178,7 +178,7 @@
 	tag.context = t->as->asid;
 	tag.vpn = pg.vpn;
-	
+
 	itlb_tag_access_write(tag.value);
-	
+
 	data.value = 0;
 	data.v = true;
@@ -190,5 +190,5 @@
 	data.w = false;
 	data.g = t->g;
-	
+
 	itlb_data_in_write(data.value);
 }
@@ -353,5 +353,5 @@
 	tlb_data_t d;
 	tlb_tag_read_reg_t t;
-	
+
 	printf("I-TLB contents:\n");
 	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
@@ -377,5 +377,5 @@
 	tlb_data_t d;
 	tlb_tag_read_reg_t t;
-	
+
 	printf("TLB_ISMALL contents:\n");
 	for (i = 0; i < tlb_ismall_size(); i++) {
@@ -384,5 +384,5 @@
 		print_tlb_entry(i, t, d);
 	}
-	
+
 	printf("TLB_IBIG contents:\n");
 	for (i = 0; i < tlb_ibig_size(); i++) {
@@ -391,5 +391,5 @@
 		print_tlb_entry(i, t, d);
 	}
-	
+
 	printf("TLB_DSMALL contents:\n");
 	for (i = 0; i < tlb_dsmall_size(); i++) {
@@ -398,5 +398,5 @@
 		print_tlb_entry(i, t, d);
 	}
-	
+
 	printf("TLB_DBIG_1 contents:\n");
 	for (i = 0; i < tlb_dbig_size(); i++) {
@@ -405,5 +405,5 @@
 		print_tlb_entry(i, t, d);
 	}
-	
+
 	printf("TLB_DBIG_2 contents:\n");
 	for (i = 0; i < tlb_dbig_size(); i++) {
@@ -423,5 +423,5 @@
 	sfsr.value = dtlb_sfsr_read();
 	sfar = dtlb_sfar_read();
-	
+
 #if defined (US)
 	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
@@ -433,7 +433,7 @@
 	    sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
 #endif
-	
+
 	printf("DTLB SFAR: address=%p\n", (void *) sfar);
-	
+
 	dtlb_sfsr_write(0);
 }
@@ -446,5 +446,5 @@
 	sfsr.value = dtlb_sfsr_read();
 	sfar = dtlb_sfar_read();
-	
+
 #if defined (US)
 	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
@@ -456,7 +456,7 @@
 	    sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
 #endif
-	    
+
 	printf("DTLB SFAR: address=%p\n", (void *) sfar);
-	
+
 	dtlb_sfsr_write(0);
 }
@@ -467,5 +467,5 @@
 {
 	int i;
-	
+
 	/*
 	 * Walk all ITLB and DTLB entries and remove all unlocked mappings.
@@ -521,17 +521,17 @@
 {
 	tlb_context_reg_t pc_save, ctx;
-	
+
 	/* switch to nucleus because we are mapped by the primary context */
 	nucleus_enter();
-	
+
 	ctx.v = pc_save.v = mmu_primary_context_read();
 	ctx.context = asid;
 	mmu_primary_context_write(ctx.v);
-	
+
 	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
 	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
-	
+
 	mmu_primary_context_write(pc_save.v);
-	
+
 	nucleus_leave();
 }
@@ -548,12 +548,12 @@
 	unsigned int i;
 	tlb_context_reg_t pc_save, ctx;
-	
+
 	/* switch to nucleus because we are mapped by the primary context */
 	nucleus_enter();
-	
+
 	ctx.v = pc_save.v = mmu_primary_context_read();
 	ctx.context = asid;
 	mmu_primary_context_write(ctx.v);
-	
+
 	for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
 		itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
@@ -562,7 +562,7 @@
 		    page + i * MMU_PAGE_SIZE);
 	}
-	
+
 	mmu_primary_context_write(pc_save.v);
-	
+
 	nucleus_leave();
 }
Index: kernel/arch/sparc64/src/mm/sun4u/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/tsb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4u/tsb.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -57,8 +57,8 @@
 	size_t i;
 	size_t cnt;
-	
+
 	assert(as->arch.itsb);
 	assert(as->arch.dtsb);
-	
+
 	i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK;
 
@@ -67,5 +67,5 @@
 	else
 		cnt = pages * 2;
-	
+
 	for (i = 0; i < cnt; i++) {
 		as->arch.itsb[(i0 + i) & ITSB_ENTRY_MASK].tag.invalid = true;
@@ -86,5 +86,5 @@
 
 	assert(index <= 1);
-	
+
 	as = t->as;
 	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK;
@@ -112,7 +112,7 @@
 	tte->data.p = t->k;	/* p as privileged, k as kernel */
 	tte->data.v = t->p;	/* v as valid, p as present */
-	
+
 	write_barrier();
-	
+
 	tte->tag.invalid = false;	/* mark the entry as valid */
 }
@@ -129,5 +129,5 @@
 	tsb_entry_t *tte;
 	size_t entry;
-	
+
 	assert(index <= 1);
 
@@ -161,7 +161,7 @@
 	tte->data.w = ro ? false : t->w;
 	tte->data.v = t->p;
-	
+
 	write_barrier();
-	
+
 	tte->tag.invalid = false;	/* mark the entry as valid */
 }
Index: kernel/arch/sparc64/src/mm/sun4v/as.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/as.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4v/as.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -79,8 +79,8 @@
 	as->arch.tsb_description.reserved = 0;
 	as->arch.tsb_description.context = 0;
-	
+
 	memsetb(tsb, TSB_SIZE, 0);
 #endif
-	
+
 	return EOK;
 }
@@ -90,5 +90,5 @@
 #ifdef CONFIG_TSB
 	frame_free(as->arch.tsb_description.tsb_base, TSB_FRAMES);
-	
+
 	return TSB_FRAMES;
 #else
@@ -102,5 +102,5 @@
 	tsb_invalidate(as, 0, (size_t) -1);
 #endif
-	
+
 	return EOK;
 }
@@ -117,11 +117,11 @@
 {
 	mmu_secondary_context_write(as->asid);
-	
+
 #ifdef CONFIG_TSB
 	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-	
+
 	assert(as->arch.tsb_description.tsb_base);
 	uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
-	
+
 	if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
 		/*
@@ -134,5 +134,5 @@
 		dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
 	}
-	
+
 	__hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&as->arch.tsb_description));
 #endif
@@ -156,12 +156,12 @@
 	 *
 	 */
-	
+
 #ifdef CONFIG_TSB
 	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-	
+
 	assert(as->arch.tsb_description.tsb_base);
-	
+
 	uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
-	
+
 	if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
 		/*
Index: kernel/arch/sparc64/src/mm/sun4v/frame.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4v/frame.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -48,5 +48,5 @@
 {
 	unsigned int i;
-		
+
 	for (i = 0; i < memmap.cnt; i++) {
 		uintptr_t base;
@@ -62,5 +62,5 @@
 		size = ALIGN_DOWN(memmap.zones[i].size -
 		    (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE);
-		
+
 		if (!frame_adjust_zone_bounds(low, &base, &size))
 			continue;
@@ -74,5 +74,5 @@
 			if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0))))
 				confdata = ADDR2PFN(KA2PA(PFN2ADDR(2)));
-			
+
 			zone_create(pfn, count, confdata,
 			    ZONE_AVAILABLE | ZONE_LOWMEM);
Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -128,5 +128,5 @@
 {
 	tte_data_t data;
-	
+
 	data.value = 0;
 	data.v = true;
@@ -143,5 +143,5 @@
 	data.w = true;
 	data.size = pagesize;
-	
+
 	if (locked) {
 		__hypercall_fast4(
@@ -163,5 +163,5 @@
 {
 	tte_data_t data;
-	
+
 	data.value = 0;
 	data.v = true;
@@ -178,5 +178,5 @@
 	data.w = ro ? false : t->w;
 	data.size = PAGESIZE_8K;
-	
+
 	__hypercall_hyperfast(
 		t->page, t->as->asid, data.value, MMU_FLAG_DTLB, 0, MMU_MAP_ADDR);
@@ -190,5 +190,5 @@
 {
 	tte_data_t data;
-	
+
 	data.value = 0;
 	data.v = true;
@@ -203,5 +203,5 @@
 	data.w = false;
 	data.size = PAGESIZE_8K;
-	
+
 	__hypercall_hyperfast(
 		t->page, t->as->asid, data.value, MMU_FLAG_ITLB, 0, MMU_MAP_ADDR);
@@ -387,5 +387,5 @@
 {
 	unsigned int i;
-	
+
 	/* switch to nucleus because we are mapped by the primary context */
 	nucleus_enter();
Index: kernel/arch/sparc64/src/mm/sun4v/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tsb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/mm/sun4v/tsb.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -59,7 +59,7 @@
 	size_t i0, i;
 	size_t cnt;
-	
+
 	assert(as->arch.tsb_description.tsb_base);
-	
+
 	i0 = (page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
 
@@ -68,5 +68,5 @@
 	else
 		cnt = pages;
-	
+
 	tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
 	for (i = 0; i < cnt; i++)
@@ -87,5 +87,5 @@
 	as = t->as;
 	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
-	
+
 	tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
 	tte = &tsb[index];
@@ -114,7 +114,7 @@
 	tte->data.w = false;
 	tte->data.size = PAGESIZE_8K;
-	
+
 	write_barrier();
-	
+
 	tte->data.v = t->p;	/* v as valid, p as present */
 }
@@ -162,7 +162,7 @@
 	tte->data.w = ro ? false : t->w;
 	tte->data.size = PAGESIZE_8K;
-	
+
 	write_barrier();
-	
+
 	tte->data.v = t->p;	/* v as valid, p as present */
 }
Index: kernel/arch/sparc64/src/proc/sun4v/scheduler.c
===================================================================
--- kernel/arch/sparc64/src/proc/sun4v/scheduler.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/proc/sun4v/scheduler.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -71,5 +71,5 @@
 		THREAD->arch.uspace_window_buffer =
 		    (uint8_t *) asi_u64_read(ASI_SCRATCHPAD, SCRATCHPAD_WBUF);
-		
+
 	}
 }
Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -97,13 +97,13 @@
 	 * we explicitly disable preemption.
 	 */
-	
+
 	preemption_disable();
-	
+
 	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
 	if (status & INTR_DISPATCH_STATUS_BUSY)
 		panic("Interrupt Dispatch Status busy bit set\n");
-	
+
 	assert(!(pstate_read() & PSTATE_IE_BIT));
-	
+
 	do {
 		set_intr_w_data(func);
@@ -111,11 +111,11 @@
 		    (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
 		    VA_INTR_W_DISPATCH, 0);
-	
+
 		membar();
-		
+
 		do {
 			status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
 		} while (status & INTR_DISPATCH_STATUS_BUSY);
-		
+
 		done = !(status & INTR_DISPATCH_STATUS_NACK);
 		if (!done) {
@@ -128,5 +128,5 @@
 		}
 	} while (!done);
-	
+
 	preemption_enable();
 }
@@ -147,7 +147,7 @@
 {
 	unsigned int i;
-	
+
 	void (* func)(void);
-	
+
 	switch (ipi) {
 	case IPI_TLB_SHOOTDOWN:
@@ -158,5 +158,5 @@
 		break;
 	}
-	
+
 	/*
 	 * As long as we don't support hot-plugging
@@ -165,5 +165,5 @@
 	 * without locking.
 	 */
-	
+
 	for (i = 0; i < config.cpu_active; i++) {
 		if (&cpus[i] == CPU)
@@ -187,5 +187,5 @@
 {
 	assert(&cpus[cpu_id] != CPU);
-	
+
 	if (ipi == IPI_SMP_CALL) {
 		cross_call(cpus[cpu_id].arch.mid, smp_call_ipi_recv);
Index: kernel/arch/sparc64/src/smp/sun4u/smp.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/smp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/smp/sun4u/smp.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -62,5 +62,5 @@
 	ofw_tree_node_t *node;
 	unsigned int cnt = 0;
-	
+
 	if (is_us() || is_us_iii()) {
 		node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
@@ -76,5 +76,5 @@
 		}
 	}
-	
+
 	config.cpu_count = max(1, cnt);
 }
@@ -89,5 +89,5 @@
 	uint32_t mid;
 	ofw_tree_property_t *prop;
-		
+
 	/* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
 	prop = ofw_tree_getprop(node, "upa-portid");
@@ -96,8 +96,8 @@
 	if ((!prop) || (!prop->value))
 		prop = ofw_tree_getprop(node, "cpuid");
-		
+
 	if (!prop || prop->value == NULL)
 		return;
-		
+
 	mid = *((uint32_t *) prop->value);
 	if (CPU->arch.mid == mid)
@@ -105,5 +105,5 @@
 
 	waking_up_mid = mid;
-		
+
 	if (waitq_sleep_timeout(&ap_completion_wq, 1000000,
 	    SYNCH_FLAGS_NONE, NULL) == ETIMEOUT)
@@ -117,5 +117,5 @@
 	ofw_tree_node_t *node;
 	int i;
-	
+
 	if (is_us() || is_us_iii()) {
 		node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
Index: kernel/arch/sparc64/src/smp/sun4v/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4v/ipi.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/smp/sun4v/ipi.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -96,5 +96,5 @@
 {
 	void (* func)(void);
-	
+
 	switch (ipi) {
 	case IPI_TLB_SHOOTDOWN:
Index: kernel/arch/sparc64/src/smp/sun4v/smp.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4v/smp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/smp/sun4v/smp.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -359,5 +359,5 @@
 	if (__hypercall_fast1(CPU_STOP, cpuid) != EOK)
 		return false;
-	
+
 	/* wait for the CPU to stop */
 	uint64_t state;
@@ -365,5 +365,5 @@
 	while (state == CPU_STATE_RUNNING)
 		__hypercall_fast_ret1(cpuid, 0, 0, 0, 0, CPU_STATE, &state);
-	
+
 	/* make the CPU run again and execute HelenOS code */
 	if (__hypercall_fast4(CPU_START, cpuid,
@@ -372,10 +372,10 @@
 		return false;
 #endif
-	
+
 	if (waitq_sleep_timeout(&ap_completion_wq, 10000000,
 	    SYNCH_FLAGS_NONE, NULL) == ETIMEOUT)
 		printf("%s: waiting for processor (cpuid = %" PRIu64 ") timed out\n",
 		    __func__, cpuid);
-	
+
 	return true;
 }
Index: kernel/arch/sparc64/src/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sparc64.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sparc64.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -79,5 +79,5 @@
 		if (options) {
 			ofw_tree_property_t *prop;
-		
+
 			prop = ofw_tree_getprop(options, "boot-args");
 			if (prop && prop->value) {
Index: kernel/arch/sparc64/src/sun4u/asm.S
===================================================================
--- kernel/arch/sparc64/src/sun4u/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4u/asm.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -102,5 +102,5 @@
 	wrpr %g1, TSTATE_IE_BIT, %tstate
 	wrpr %i0, 0, %tnpc
-	
+
 	/*
 	 * Set primary context according to secondary context.
@@ -117,5 +117,5 @@
 	 */
 	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
-	
+
 	done				! jump to userspace
 FUNCTION_END(switch_to_userspace)
Index: kernel/arch/sparc64/src/sun4u/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sun4u/sparc64.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4u/sparc64.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -72,5 +72,5 @@
 	/* Copy init task info. */
 	init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
-	
+
 	size_t i;
 	for (i = 0; i < init.cnt; i++) {
@@ -80,5 +80,5 @@
 		    bootinfo->taskmap.tasks[i].name);
 	}
-	
+
 	/* Copy physical memory map. */
 	memmap.total = bootinfo->memmap.total;
@@ -88,9 +88,9 @@
 		memmap.zones[i].size = bootinfo->memmap.zones[i].size;
 	}
-	
+
 	/* Copy boot allocations info. */
 	ballocs.base = bootinfo->ballocs.base;
 	ballocs.size = bootinfo->ballocs.size;
-	
+
 	ofw_tree_init(bootinfo->ofw_root);
 }
@@ -111,5 +111,5 @@
 		/* Map OFW information into sysinfo */
 		ofw_sysinfo_map();
-		
+
 		/*
 		 * We have 2^11 different interrupt vectors.
@@ -167,5 +167,5 @@
 	    (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS),
 	    (uintptr_t) kernel_uarg->uspace_uarg);
-	
+
 	/* Not reached */
 	while (1);
Index: kernel/arch/sparc64/src/sun4u/start.S
===================================================================
--- kernel/arch/sparc64/src/sun4u/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4u/start.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -85,5 +85,5 @@
 	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
 	srlx %l6, 13, %l5
-	
+
 	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
 	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
@@ -101,5 +101,5 @@
 	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
 						! traps for kernel
-						
+
 	wrpr %g0, 0, %wstate			! use default spill/fill trap
 
@@ -132,5 +132,5 @@
 	set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \
 		TLB_DEMAP_CONTEXT_SHIFT), %r1
-	
+
 	! demap context 0
 	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
@@ -161,5 +161,5 @@
 	sllx %r2, TTE_V_SHIFT, %r2; \
 	or %r1, %r2, %r1;
-	
+
 	! write DTLB data and install the kernel mapping
 	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
@@ -182,5 +182,5 @@
 	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
 	membar #Sync
-	
+
 	/*
 	 * Now is time to take over the IMMU. Unfortunatelly, it cannot be done
@@ -202,7 +202,7 @@
 	 * the taken over DTLB.
 	 */
-	
+
 	set kernel_image_start, %g5
-	
+
 	! write ITLB tag of context 1
 	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
@@ -215,15 +215,15 @@
 	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
 	flush %g5
-	
+
 	! switch to context 1
 	mov MEM_CONTEXT_TEMP, %g1
 	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
 	flush %g5
-	
+
 	! demap context 0
 	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
 	stxa %g0, [%g1] ASI_IMMU_DEMAP
 	flush %g5
-	
+
 	! write ITLB tag of context 0
 	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
@@ -244,9 +244,9 @@
 	stxa %g0, [%g1] ASI_IMMU_DEMAP
 	flush %g5
-	
+
 	! set context 0 in the primary context register
 	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
 	flush %g5
-	
+
 	! leave nucleus - using primary context, i.e. context 0
 	wrpr %g0, 0, %tl
@@ -271,9 +271,9 @@
 	or %l3, %l5, %l3
 	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
-	
+
 	! flush the whole D-cache
 	set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1
 	stxa %g0, [%g1] ASI_DCACHE_TAG
-	
+
 0:
 	membar #Sync
@@ -282,5 +282,5 @@
 	stxa %g0, [%g1] ASI_DCACHE_TAG
 	membar #Sync
-	
+
 	/*
 	 * So far, we have not touched the stack.
@@ -290,5 +290,5 @@
 	or %sp, %lo(temporary_boot_stack), %sp
 	sub %sp, STACK_BIAS, %sp
-	
+
 	/*
 	 * Call sparc64_pre_main(bootinfo)
@@ -296,5 +296,5 @@
 	call sparc64_pre_main
 	mov %o1, %o0
-	
+
 	/*
 	 * Create the first stack frame.
@@ -372,5 +372,5 @@
 	/* Not reached. */
 #endif
-	
+
 0:
 	ba,a %xcc, 0b
Index: kernel/arch/sparc64/src/sun4v/asm.S
===================================================================
--- kernel/arch/sparc64/src/sun4v/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4v/asm.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -58,5 +58,5 @@
 	wrpr %g1, TSTATE_IE_BIT, %tstate
 	wrpr %i0, 0, %tnpc
-	
+
 	/*
 	 * Set primary context according to secondary context.
Index: kernel/arch/sparc64/src/sun4v/md.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/md.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4v/md.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -244,5 +244,5 @@
 		char *head;
 		more = str_parse_head(&name, &head);
-		
+
 		while (md_next_child(&node)) {
 			element_idx_t child = md_get_child_node(node);
@@ -292,5 +292,5 @@
 			return true;
 		}
-		
+
 		(*node)++;
 	} while (element->tag != LIST_END);
Index: kernel/arch/sparc64/src/sun4v/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/sparc64.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4v/sparc64.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -74,5 +74,5 @@
 	/* Copy init task info. */
 	init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
-	
+
 	size_t i;
 	for (i = 0; i < init.cnt; i++) {
@@ -82,5 +82,5 @@
 		    bootinfo->taskmap.tasks[i].name);
 	}
-	
+
 	/* Copy physical memory map. */
 	memmap.total = bootinfo->memmap.total;
@@ -90,5 +90,5 @@
 		memmap.zones[i].size = bootinfo->memmap.zones[i].size;
 	}
-	
+
 	md_init();
 }
@@ -109,5 +109,5 @@
 		/* Map OFW information into sysinfo */
 		ofw_sysinfo_map();
-		
+
 		/*
 		 * We have 2^11 different interrupt vectors.
@@ -165,5 +165,5 @@
 	    (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS),
 	    (uintptr_t) kernel_uarg->uspace_uarg);
-	
+
 	/* Not reached */
 	while (1);
Index: kernel/arch/sparc64/src/sun4v/start.S
===================================================================
--- kernel/arch/sparc64/src/sun4v/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/sun4v/start.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -115,5 +115,5 @@
 	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
 	srlx %l6, 13, %l5
-	
+
 	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
 	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
@@ -130,5 +130,5 @@
 	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
 						! traps for kernel
-						
+
 	wrpr %g0, 0, %wstate			! use default spill/fill trap
 
@@ -252,5 +252,5 @@
 	call sparc64_pre_main
 	or %l1, %g0, %o0
-	
+
 	/*
 	 * Create the first stack frame.
Index: kernel/arch/sparc64/src/trap/exception.c
===================================================================
--- kernel/arch/sparc64/src/trap/exception.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/trap/exception.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -48,5 +48,5 @@
 	const char *tpcs = symtab_fmt_name_lookup(istate->tpc);
 	const char *tnpcs = symtab_fmt_name_lookup(istate->tnpc);
-	
+
 	printf("TSTATE=%#" PRIx64 "\n", istate->tstate);
 	printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, tpcs);
@@ -100,5 +100,5 @@
 {
 	fprs_reg_t fprs;
-	
+
 	fprs.value = fprs_read();
 	if (!fprs.fef) {
Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/sun4u/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -58,5 +58,5 @@
 	if (status & (!INTR_DISPATCH_STATUS_BUSY))
 		panic("Interrupt Dispatch Status busy bit not set\n");
-	
+
 	uint64_t intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
 #if defined (US)
@@ -65,5 +65,5 @@
 	uint64_t data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0);
 #endif
-	
+
 	irq_t *irq = irq_dispatch_and_lock(data0);
 	if (irq) {
@@ -72,5 +72,5 @@
 		 */
 		irq->handler(irq);
-		
+
 		/*
 		 * See if there is a clear-interrupt-routine and call it.
@@ -78,5 +78,5 @@
 		if (irq->cir)
 			irq->cir(irq->cir_arg, irq->inr);
-		
+
 		irq_spinlock_unlock(&irq->lock, false);
 	} else if (data0 > config.base) {
@@ -103,5 +103,5 @@
 #endif
 	}
-	
+
 	membar();
 	asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
Index: kernel/arch/sparc64/src/trap/sun4u/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/sun4u/trap_table.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/trap/sun4u/trap_table.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -502,5 +502,5 @@
 .if NOT(\is_syscall)
 	rdpr %tstate, %g3
-	
+
 	/*
 	 * One of the ways this handler can be invoked is after a nested MMU trap from
@@ -576,5 +576,5 @@
 	 */
 	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
-	
+
 	/*
 	 * Copy arguments.
@@ -605,9 +605,9 @@
 	 */
 	stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
-	
+
 	wrpr %g0, 0, %tl
 	wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
 	SAVE_GLOBALS
-	
+
 .if NOT(\is_syscall)
 	/*
@@ -629,5 +629,5 @@
 	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
 	wrpr %g0, 1, %tl
-	
+
 	/*
 	 * Read TSTATE, TPC and TNPC from saved copy.
@@ -742,5 +742,5 @@
 	rd %pc, %g1
 	flush %g1
-	
+
 	rdpr %cwp, %g1
 	rdpr %otherwin, %g2
@@ -800,5 +800,5 @@
 	mov NWINDOWS - 2, %g1			! use dealy slot for both cases
 	sub %g1, %g2, %g1
-	
+
 	wrpr %g0, 0, %otherwin
 	wrpr %g1, 0, %cansave			! NWINDOWS - 2 - CANRESTORE
@@ -845,5 +845,5 @@
 	and %g1, NWINDOWS - 1, %g1
 	wrpr %g1, 0, %cwp			! CWP--
-	
+
 .if \is_syscall
 	done
Index: kernel/arch/sparc64/src/trap/sun4v/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/sun4v/trap_table.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/src/trap/sun4v/trap_table.S	(revision a1a81f698d5d7a69659be156314cb47101fde090)
@@ -606,5 +606,5 @@
 	and \tmpreg1, NWINDOWS - 1, \tmpreg1		! modulo NWINDOWS
 	wrpr \tmpreg1, %cwp
-	
+
 	! spill to kernel stack
 	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
@@ -766,5 +766,5 @@
 	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
 	wr %g4, %y
-	
+
 	/* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */
 	and %g1, TSTATE_CWP_MASK, %l0
@@ -871,5 +871,5 @@
 	and \tmpreg1, NWINDOWS - 1, \tmpreg1		! modulo NWINDOWS
 	wrpr \tmpreg1, %cwp
-	
+
 	! spill to userspace window buffer
 	SAVE_TO_USPACE_WBUF \tmpreg3, \tmpreg1
@@ -1028,5 +1028,5 @@
 	mov NWINDOWS - 2, %g1			! use dealy slot for both cases
 	sub %g1, %g2, %g1
-	
+
 	wrpr %g0, 0, %otherwin
 	wrpr %g1, 0, %cansave			! NWINDOWS - 2 - CANRESTORE
@@ -1073,5 +1073,5 @@
 	and %g1, NWINDOWS - 1, %g1
 	wrpr %g1, 0, %cwp			! CWP--
-	
+
 .if \is_syscall
 	done