Changeset a03b609 in mainline for kernel/arch/arm32/src

Timestamp:

2013-01-19T18:17:27Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

26e3db2

Parents:

827aae5

Message:

arm32: Convert sctlr use to cp15 helpers.

Location:

kernel/arch/arm32/src

Files:

• cpu/cpu.c (modified) (4 diffs)
• exception.c (modified) (2 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -129 +129 @@
 void cpu_arch_init(void)
 {
-        /* Get rid of any boot code hiding in ICache
-         * This is safe without regards to ICache state. */
-        memory_barrier();
-        smc_coherence();
-
-        uint32_t control_reg = 0;
-        asm volatile (
-                "mrc p15, 0, %[control_reg], c1, c0"
-                : [control_reg] "=r" (control_reg)
-        );
+        uint32_t control_reg = SCTLR_read();
         
         /* Turn off tex remap, RAZ/WI prior to armv7 */
-        control_reg &= ~CP15_R1_TEX_REMAP_EN;
+        control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
         /* Turn off accessed flag, RAZ/WI prior to armv7 */
-        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
+        control_reg &= ~(SCTLR_ACCESS_FLAG_EN_FLAG | SCTLR_HW_ACCESS_FLAG_EN_FLAG);
         /* Disable branch prediction RAZ/WI if not supported */
-        control_reg &= ~CP15_R1_BRANCH_PREDICT_EN;
+        control_reg &= ~SCTLR_BRANCH_PREDICT_EN_FLAG;
 
         /* Unaligned access is supported on armv6+ */
@@ -153 +144 @@
          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
          * L.3.1 (p. 2456) */
-        control_reg |= CP15_R1_UNALIGNED_EN;
+        control_reg |= SCTLR_UNALIGNED_EN_FLAG;
         /* Disable alignment checks, this turns unaligned access to undefined,
          * unless U bit is set. */
-        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
+        control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
         /* Enable caching, On arm prior to armv7 there is only one level
          * of caches. Data cache is coherent.
@@ -167 +158 @@
          * L2 Cache for armv7 was enabled in boot code.
          */
-        control_reg |= CP15_R1_CACHE_EN;
+        control_reg |= SCTLR_CACHE_EN_FLAG;
 #endif
 #ifdef PROCESSOR_cortex_a8
@@ -173 +164 @@
           * Cortex-A8 implements IVIPT extension.
           * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
-        control_reg |= CP15_R1_INST_CACHE_EN;
-#endif
-        
-        asm volatile (
-                "mcr p15, 0, %[control_reg], c1, c0"
-                :: [control_reg] "r" (control_reg)
-        );
+        control_reg |= SCTLR_INST_CACHE_EN_FLAG;
+#endif
+        SCTLR_write(control_reg);
+
 #ifdef CONFIG_FPU
         fpu_setup();

kernel/arch/arm32/src/exception.c

@@ -39 +39 @@
 #include <interrupt.h>
 #include <arch/mm/page_fault.h>
+#include <arch/cp15.h>
 #include <arch/barrier.h>
 #include <print.h>
@@ -136 +137 @@
 static void high_vectors(void)
 {
-        uint32_t control_reg = 0;
-        asm volatile (
-                "mrc p15, 0, %[control_reg], c1, c0"
-                : [control_reg] "=r" (control_reg)
-        );
+        uint32_t control_reg = SCTLR_read();
         
         /* switch on the high vectors bit */
-        control_reg |= CP15_R1_HIGH_VECTORS_EN;
-        
-        asm volatile (
-                "mcr p15, 0, %[control_reg], c1, c0"
-                :: [control_reg] "r" (control_reg)
-        );
+        control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
+        
+        SCTLR_write(control_reg);
 }
 #endif