Changeset 9ad03fe in mainline for arch/ia64/include

Timestamp:

2006-03-01T12:58:13Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03427d0

Parents:

a0d74fd

Message:

ia64 work.
More capable TLB miss handlers.
The ia64 kernel now passes mm/mapping1 test.

Fix generic hash table to properly initialize lists.

Change page_ht() to properly initialize inserted PTE's.
Change format of generic page hash table PTE's.

File:

• arch/ia64/include/mm/tlb.h (modified) (1 diff)

arch/ia64/include/mm/tlb.h

@@ -78 +78 @@
 extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
 
-extern void dtlb_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
+extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
+
+extern void dtc_pte_copy(pte_t *t);
+extern void itc_pte_copy(pte_t *t);
 
 extern void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate);