Changeset 99d6fd0 in mainline for kernel/arch/amd64/src


Ignore:
Timestamp:
2009-03-13T12:57:15Z (16 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
421c833
Parents:
0160b1c8
Message:

cleanup pm.h and related stuff (no change in functionality)

Location:
kernel/arch/amd64/src
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/amd64/src/ddi/ddi.c

    r0160b1c8 r99d6fd0  
    5858{
    5959        count_t bits;
    60 
     60       
    6161        bits = ioaddr + size;
    6262        if (bits > IO_PORTS)
    6363                return ENOENT;
    64 
     64       
    6565        if (task->arch.iomap.bits < bits) {
    6666                bitmap_t oldiomap;
    6767                uint8_t *newmap;
    68        
     68               
    6969                /*
    7070                 * The I/O permission bitmap is too small and needs to be grown.
     
    7878                    task->arch.iomap.bits);
    7979                bitmap_initialize(&task->arch.iomap, newmap, bits);
    80 
     80               
    8181                /*
    8282                 * Mark the new range inaccessible.
     
    8484                bitmap_set_range(&task->arch.iomap, oldiomap.bits,
    8585                    bits - oldiomap.bits);
    86 
     86               
    8787                /*
    8888                 * In case there really existed smaller iomap,
    8989                 * copy its contents and deallocate it.
    90                  */             
     90                 */
    9191                if (oldiomap.bits) {
    9292                        bitmap_copy(&task->arch.iomap, &oldiomap,
     
    9595                }
    9696        }
    97 
     97       
    9898        /*
    9999         * Enable the range and we are done.
    100100         */
    101101        bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size);
    102 
     102       
    103103        /*
    104104         * Increment I/O Permission bitmap generation counter.
    105105         */
    106106        task->arch.iomapver++;
    107 
     107       
    108108        return 0;
    109109}
     
    123123        tss_descriptor_t *tss_desc;
    124124        count_t ver;
    125 
     125       
    126126        /* First, copy the I/O Permission Bitmap. */
    127127        spinlock_lock(&TASK->lock);
     
    141141        }
    142142        spinlock_unlock(&TASK->lock);
    143 
     143       
    144144        /*
    145145         * Second, adjust TSS segment limit.
     
    152152       
    153153        /*
    154         * Before we load new TSS limit, the current TSS descriptor
    155         * type must be changed to describe inactive TSS.
    156         */
    157         tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
     154        * Before we load new TSS limit, the current TSS descriptor
     155        * type must be changed to describe inactive TSS.
     156        */
     157        tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
    158158        tss_desc->type = AR_TSS;
    159159        tr_load(gdtselector(TSS_DES));
  • kernel/arch/amd64/src/pm.c

    r0160b1c8 r99d6fd0  
    138138void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
    139139{
    140         struct tss_descriptor *td = (tss_descriptor_t *) d;
    141 
     140        tss_descriptor_t *td = (tss_descriptor_t *) d;
     141       
    142142        td->limit_0_15 = limit & 0xffff;
    143143        td->limit_16_19 = (limit >> 16) & 0xf;
     
    186186void pm_init(void)
    187187{
    188         descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
     188        descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
    189189        tss_descriptor_t *tss_desc;
    190 
     190       
    191191        /*
    192192         * Each CPU has its private GDT and TSS.
    193193         * All CPUs share one IDT.
    194194         */
    195 
     195       
    196196        if (config.cpu_active == 1) {
    197197                idt_init();
     
    201201                 */
    202202                tss_p = &tss;
    203         }
    204         else {
     203        } else {
    205204                /* We are going to use malloc, which may return
    206205                 * non boot-mapped pointer, initialize the CR3 register
    207206                 * ahead of page_init */
    208207                write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
    209 
    210                 tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
     208               
     209                tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
    211210                if (!tss_p)
    212211                        panic("Cannot allocate TSS.");
    213212        }
    214 
     213       
    215214        tss_initialize(tss_p);
    216 
     215       
    217216        tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
    218217        tss_desc->present = 1;
     
    222221        gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
    223222        gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
    224 
     223       
    225224        gdtr_load(&gdtr);
    226225        idtr_load(&idtr);
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