Changeset 99d6fd0 in mainline for kernel/arch/amd64/src
- Timestamp:
- 2009-03-13T12:57:15Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 421c833
- Parents:
- 0160b1c8
- Location:
- kernel/arch/amd64/src
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/ddi/ddi.c
r0160b1c8 r99d6fd0 58 58 { 59 59 count_t bits; 60 60 61 61 bits = ioaddr + size; 62 62 if (bits > IO_PORTS) 63 63 return ENOENT; 64 64 65 65 if (task->arch.iomap.bits < bits) { 66 66 bitmap_t oldiomap; 67 67 uint8_t *newmap; 68 68 69 69 /* 70 70 * The I/O permission bitmap is too small and needs to be grown. … … 78 78 task->arch.iomap.bits); 79 79 bitmap_initialize(&task->arch.iomap, newmap, bits); 80 80 81 81 /* 82 82 * Mark the new range inaccessible. … … 84 84 bitmap_set_range(&task->arch.iomap, oldiomap.bits, 85 85 bits - oldiomap.bits); 86 86 87 87 /* 88 88 * In case there really existed smaller iomap, 89 89 * copy its contents and deallocate it. 90 */ 90 */ 91 91 if (oldiomap.bits) { 92 92 bitmap_copy(&task->arch.iomap, &oldiomap, … … 95 95 } 96 96 } 97 97 98 98 /* 99 99 * Enable the range and we are done. 100 100 */ 101 101 bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size); 102 102 103 103 /* 104 104 * Increment I/O Permission bitmap generation counter. 105 105 */ 106 106 task->arch.iomapver++; 107 107 108 108 return 0; 109 109 } … … 123 123 tss_descriptor_t *tss_desc; 124 124 count_t ver; 125 125 126 126 /* First, copy the I/O Permission Bitmap. */ 127 127 spinlock_lock(&TASK->lock); … … 141 141 } 142 142 spinlock_unlock(&TASK->lock); 143 143 144 144 /* 145 145 * Second, adjust TSS segment limit. … … 152 152 153 153 /* 154 155 156 157 tss_desc = (tss_descriptor_t *) 154 * Before we load new TSS limit, the current TSS descriptor 155 * type must be changed to describe inactive TSS. 156 */ 157 tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES]; 158 158 tss_desc->type = AR_TSS; 159 159 tr_load(gdtselector(TSS_DES)); -
kernel/arch/amd64/src/pm.c
r0160b1c8 r99d6fd0 138 138 void gdt_tss_setlimit(descriptor_t *d, uint32_t limit) 139 139 { 140 struct tss_descriptor*td = (tss_descriptor_t *) d;141 140 tss_descriptor_t *td = (tss_descriptor_t *) d; 141 142 142 td->limit_0_15 = limit & 0xffff; 143 143 td->limit_16_19 = (limit >> 16) & 0xf; … … 186 186 void pm_init(void) 187 187 { 188 descriptor_t *gdt_p = ( struct descriptor*) gdtr.base;188 descriptor_t *gdt_p = (descriptor_t *) gdtr.base; 189 189 tss_descriptor_t *tss_desc; 190 190 191 191 /* 192 192 * Each CPU has its private GDT and TSS. 193 193 * All CPUs share one IDT. 194 194 */ 195 195 196 196 if (config.cpu_active == 1) { 197 197 idt_init(); … … 201 201 */ 202 202 tss_p = &tss; 203 } 204 else { 203 } else { 205 204 /* We are going to use malloc, which may return 206 205 * non boot-mapped pointer, initialize the CR3 register 207 206 * ahead of page_init */ 208 207 write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); 209 210 tss_p = ( struct tss*) malloc(sizeof(tss_t), FRAME_ATOMIC);208 209 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); 211 210 if (!tss_p) 212 211 panic("Cannot allocate TSS."); 213 212 } 214 213 215 214 tss_initialize(tss_p); 216 215 217 216 tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); 218 217 tss_desc->present = 1; … … 222 221 gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); 223 222 gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); 224 223 225 224 gdtr_load(&gdtr); 226 225 idtr_load(&idtr);
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