Changeset 985e26d2 in mainline for kernel/arch/amd64/src

Timestamp:

2010-01-07T19:06:59Z (16 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8190e63

Parents:

743e17b (diff), eca2435 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

kernel/arch/amd64/src

Files:

• amd64.c (modified) (3 diffs)
• cpu/cpu.c (modified) (2 diffs)
• interrupt.c (modified) (2 diffs)

kernel/arch/amd64/src/amd64.c

@@ -67 +67 @@
 #include <ddi/irq.h>
 #include <sysinfo/sysinfo.h>
+#include <memstr.h>
 
 /** Disable I/O on non-privileged levels
@@ -211 +212 @@
                         i8042_wire(i8042_instance, kbrd);
                         trap_virtual_enable_irqs(1 << IRQ_KBD);
+                        trap_virtual_enable_irqs(1 << IRQ_MOUSE);
                 }
         }
@@ -218 +220 @@
          * self-sufficient.
          */
-        sysinfo_set_item_val("kbd", NULL, true);
-        sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
-        sysinfo_set_item_val("kbd.address.physical", NULL,
+        sysinfo_set_item_val("i8042", NULL, true);
+        sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD);
+        sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE);
+        sysinfo_set_item_val("i8042.address.physical", NULL,
             (uintptr_t) I8042_BASE);
-        sysinfo_set_item_val("kbd.address.kernel", NULL,
+        sysinfo_set_item_val("i8042.address.kernel", NULL,
             (uintptr_t) I8042_BASE);
 #endif

kernel/arch/amd64/src/cpu/cpu.c

@@ -130 +130 @@
         CPU->arch.vendor = VendorUnknown;
         if (has_cpuid()) {
-                cpuid(0, &info);
+                cpuid(INTEL_CPUID_LEVEL, &info);
 
                 /*
@@ -150 +150 @@
                 }
                                 
-                cpuid(1, &info);
+                cpuid(INTEL_CPUID_STANDARD, &info);
                 CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
                 CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;

kernel/arch/amd64/src/interrupt.c

@@ -98 +98 @@
 }
 
+static void de_fault(int n, istate_t *istate)
+{
+        fault_if_from_uspace(istate, "Divide error.");
+        decode_istate(n, istate);
+        panic("Divide error.");
+}
+
 /** General Protection Fault. */
 static void gp_fault(int n, istate_t *istate)
@@ -200 +207 @@
         }
         
+        exc_register(0, "de_fault", (iroutine) de_fault);
         exc_register(7, "nm_fault", (iroutine) nm_fault);
         exc_register(12, "ss_fault", (iroutine) ss_fault);