Changeset 985e26d2 in mainline for kernel/arch


Ignore:
Timestamp:
2010-01-07T19:06:59Z (16 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8190e63
Parents:
743e17b (diff), eca2435 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch
Files:
2 added
2 deleted
40 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/Makefile.inc

    r743e17b r985e26d2  
    3434BFD = binary
    3535TARGET = amd64-linux-gnu
     36CLANG_ARCH = x86_64
    3637TOOLCHAIN_DIR = $(CROSS_PREFIX)/amd64
    3738

  • kernel/arch/amd64/include/mm/page.h

    r743e17b r985e26d2  
    177177#define PFERR_CODE_ID           (1 << 4)
    178178
    179 static inline int get_pt_flags(pte_t *pt, size_t i)
     179/** Page Table Entry. */
     180typedef struct {
     181        unsigned present : 1;
     182        unsigned writeable : 1;
     183        unsigned uaccessible : 1;
     184        unsigned page_write_through : 1;
     185        unsigned page_cache_disable : 1;
     186        unsigned accessed : 1;
     187        unsigned dirty : 1;
     188        unsigned unused: 1;
     189        unsigned global : 1;
     190        unsigned soft_valid : 1;                /**< Valid content even if present bit is cleared. */
     191        unsigned avl : 2;
     192        unsigned addr_12_31 : 30;
     193        unsigned addr_32_51 : 21;
     194        unsigned no_execute : 1;
     195} __attribute__ ((packed)) pte_t;
     196
     197static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    180198{
    181199        pte_t *p = &pt[i];

  • kernel/arch/amd64/include/types.h

    r743e17b r985e26d2  
    8282#define PRIxn "llx"
    8383
    84 /** Page Table Entry. */
    85 typedef struct {
    86         unsigned present : 1;
    87         unsigned writeable : 1;
    88         unsigned uaccessible : 1;
    89         unsigned page_write_through : 1;
    90         unsigned page_cache_disable : 1;
    91         unsigned accessed : 1;
    92         unsigned dirty : 1;
    93         unsigned unused: 1;
    94         unsigned global : 1;
    95         unsigned soft_valid : 1;                /**< Valid content even if present bit is cleared. */
    96         unsigned avl : 2;
    97         unsigned addr_12_31 : 30;
    98         unsigned addr_32_51 : 21;
    99         unsigned no_execute : 1;
    100 } __attribute__ ((packed)) pte_t;
    101 
    10284#endif
    10385

  • kernel/arch/amd64/src/amd64.c

    r743e17b r985e26d2  
    6767#include <ddi/irq.h>
    6868#include <sysinfo/sysinfo.h>
     69#include <memstr.h>
    6970
    7071/** Disable I/O on non-privileged levels
    … …  
    211212                        i8042_wire(i8042_instance, kbrd);
    212213                        trap_virtual_enable_irqs(1 << IRQ_KBD);
     214                        trap_virtual_enable_irqs(1 << IRQ_MOUSE);
    213215                }
    214216        }
    … …  
    218220         * self-sufficient.
    219221         */
    220         sysinfo_set_item_val("kbd", NULL, true);
    221         sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
    222         sysinfo_set_item_val("kbd.address.physical", NULL,
     222        sysinfo_set_item_val("i8042", NULL, true);
     223        sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD);
     224        sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE);
     225        sysinfo_set_item_val("i8042.address.physical", NULL,
    223226            (uintptr_t) I8042_BASE);
    224         sysinfo_set_item_val("kbd.address.kernel", NULL,
     227        sysinfo_set_item_val("i8042.address.kernel", NULL,
    225228            (uintptr_t) I8042_BASE);
    226229#endif

  • kernel/arch/amd64/src/cpu/cpu.c

    r743e17b r985e26d2  
    130130        CPU->arch.vendor = VendorUnknown;
    131131        if (has_cpuid()) {
    132                 cpuid(0, &info);
     132                cpuid(INTEL_CPUID_LEVEL, &info);
    133133
    134134                /*
    … …  
    150150                }
    151151                               
    152                 cpuid(1, &info);
     152                cpuid(INTEL_CPUID_STANDARD, &info);
    153153                CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
    154154                CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;

  • kernel/arch/amd64/src/interrupt.c

    r743e17b r985e26d2  
    9898}
    9999
     100static void de_fault(int n, istate_t *istate)
     101{
     102        fault_if_from_uspace(istate, "Divide error.");
     103        decode_istate(n, istate);
     104        panic("Divide error.");
     105}
     106
    100107/** General Protection Fault. */
    101108static void gp_fault(int n, istate_t *istate)
    … …  
    200207        }
    201208       
     209        exc_register(0, "de_fault", (iroutine) de_fault);
    202210        exc_register(7, "nm_fault", (iroutine) nm_fault);
    203211        exc_register(12, "ss_fault", (iroutine) ss_fault);

  • kernel/arch/arm32/Makefile.inc

    r743e17b r985e26d2  
    6161        arch/$(KARCH)/src/mm/page.c \
    6262        arch/$(KARCH)/src/mm/tlb.c \
    63         arch/$(KARCH)/src/mm/page_fault.c
     63        arch/$(KARCH)/src/mm/page_fault.c \
     64        arch/$(KARCH)/src/ras.c
    6465
    6566ifeq ($(MACHINE),testarm)

  • kernel/arch/arm32/include/atomic.h

    r743e17b r985e26d2  
    3737#define KERN_arm32_ATOMIC_H_
    3838
     39#include <arch/asm.h>
     40
    3941/** Atomic addition.
    4042 *
    … …  
    4749static inline long atomic_add(atomic_t *val, int i)
    4850{
    49         int ret;
    50         volatile long *mem = &(val->count);
    51        
    52         asm volatile (
    53                 "1:\n"
    54                         "ldr r2, [%[mem]]\n"
    55                         "add r3, r2, %[i]\n"
    56                         "str r3, %[ret]\n"
    57                         "swp r3, r3, [%[mem]]\n"
    58                         "cmp r3, r2\n"
    59                         "bne 1b\n"
    60                 : [ret] "=m" (ret)
    61                 : [mem] "r" (mem), [i] "r" (i)
    62                 : "r3", "r2"
    63         );
     51        long ret;
     52
     53        /*
     54         * This implementation is for UP pre-ARMv6 systems where we do not have
     55         * the LDREX and STREX instructions.
     56         */
     57        ipl_t ipl = interrupts_disable();
     58        val->count += i;
     59        ret = val->count;
     60        interrupts_restore(ipl);
    6461       
    6562        return ret;

  • kernel/arch/arm32/include/mm/as.h

    r743e17b r985e26d2  
    5454#define as_destructor_arch(as)                  (as != as)
    5555#define as_create_arch(as, flags)               (as != as)
    56 #define as_install_arch(as)
    5756#define as_deinstall_arch(as)
    5857#define as_invalidate_translation_cache(as, page, cnt)

  • kernel/arch/arm32/include/mm/page.h

    r743e17b r985e26d2  
    7575/* Get PTE address accessors for each level. */
    7676#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    77         ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
     77        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    7878#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    7979        (ptl1)
    … …  
    8181        (ptl2)
    8282#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    83         ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
     83        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    8484
    8585/* Set PTE address accessors for each level. */
    8686#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    87         (set_ptl0_addr((pte_level0_t *) (ptl0)))
     87        (set_ptl0_addr((pte_t *) (ptl0)))
    8888#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    89         (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
     89        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    9090#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    9191#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    9292#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    93         (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
     93        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    9494
    9595/* Get PTE flags accessors for each level. */
    9696#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    97         get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i))
     97        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    9898#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    9999        PAGE_PRESENT
    … …  
    101101        PAGE_PRESENT
    102102#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    103         get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i))
     103        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    104104
    105105/* Set PTE flags accessors for each level. */
    106106#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    107         set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x))
     107        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    108108#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    109109#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    110110#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    111         set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x))
     111        set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
    112112
    113113/* Macros for querying the last-level PTE entries. */
    … …  
    115115        (*((uint32_t *) (pte)) != 0)
    116116#define PTE_PRESENT_ARCH(pte) \
    117         (((pte_level0_t *) (pte))->descriptor_type != 0)
     117        (((pte_t *) (pte))->l0.descriptor_type != 0)
    118118#define PTE_GET_FRAME_ARCH(pte) \
    119         (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
     119        (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
    120120#define PTE_WRITABLE_ARCH(pte) \
    121         (((pte_level1_t *) (pte))->access_permission_0 == \
    122             PTE_AP_USER_RW_KERNEL_RW)
     121        (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
    123122#define PTE_EXECUTABLE_ARCH(pte) \
    124123        1
    … …  
    159158} ATTRIBUTE_PACKED pte_level1_t;
    160159
     160typedef union {
     161        pte_level0_t l0;
     162        pte_level1_t l1;
     163} pte_t;
    161164
    162165/* Level 1 page tables access permissions */
    … …  
    191194 * @param pt    Pointer to the page table to set.
    192195 */   
    193 static inline void set_ptl0_addr(pte_level0_t *pt)
     196static inline void set_ptl0_addr(pte_t *pt)
    194197{
    195198        asm volatile (
    … …  
    205208 *  @param i      Index of the entry to return.
    206209 */
    207 static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i)
    208 {
    209         pte_level0_t *p = &pt[i];
     210static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     211{
     212        pte_level0_t *p = &pt[i].l0;
    210213        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    211214
    … …  
    220223 *  @param i      Index of the entry to return.
    221224 */
    222 static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i)
    223 {
    224         pte_level1_t *p = &pt[i];
     225static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     226{
     227        pte_level1_t *p = &pt[i].l1;
    225228
    226229        int dt = p->descriptor_type;
    … …  
    245248 *  @param flags  new flags
    246249 */
    247 static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags)
    248 {
    249         pte_level0_t *p = &pt[i];
     250static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     251{
     252        pte_level0_t *p = &pt[i].l0;
    250253
    251254        if (flags & PAGE_NOT_PRESENT) {
    … …  
    273276 *  @param flags  New flags.
    274277 */ 
    275 static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags)
    276 {
    277         pte_level1_t *p = &pt[i];
     278static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     279{
     280        pte_level1_t *p = &pt[i].l1;
    278281       
    279282        if (flags & PAGE_NOT_PRESENT) {

  • kernel/arch/arm32/include/types.h

    r743e17b r985e26d2  
    8787#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8888
    89 /** Page table entry.
    90  *
    91  *  We have different structs for level 0 and level 1 page table entries.
    92  *  See page.h for definition of pte_level*_t.
    93  */
    94 typedef struct {
    95         unsigned dummy : 32;
    96 } pte_t;
    97 
    9889#endif
    9990

  • kernel/arch/arm32/src/arm32.c

    r743e17b r985e26d2  
    4848#include <macros.h>
    4949#include <string.h>
     50#include <arch/ras.h>
    5051
    5152#ifdef MACHINE_testarm
    … …  
    8889        exception_init();
    8990        interrupt_init();
     91
     92        /* Initialize Restartable Atomic Sequences support. */
     93        ras_init();
    9094       
    9195        machine_output_init();
    … …  
    136140        uint8_t *stck;
    137141       
    138         tlb_invalidate_all();
    139142        stck = &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA];
    140143        supervisor_sp = (uintptr_t) stck;

  • kernel/arch/arm32/src/exc_handler.S

    r743e17b r985e26d2  
    148148        mov r0, #0
    149149        mov r1, r13
    150         bl exc_dispatch
     150        bl ras_check
    151151        LOAD_REGS_FROM_STACK
    152152
    … …  
    156156        mov r0, #5
    157157        mov r1, r13
    158         bl exc_dispatch
     158        bl ras_check
    159159        LOAD_REGS_FROM_STACK
    160160
    … …  
    164164        mov r0, #6
    165165        mov r1, r13
    166         bl exc_dispatch
     166        bl ras_check
    167167        LOAD_REGS_FROM_STACK
    168168
    … …  
    171171        mov r0, #1
    172172        mov r1, r13
    173         bl exc_dispatch
     173        bl ras_check
    174174        LOAD_REGS_FROM_STACK
    175175
    … …  
    179179        mov r0, #3
    180180        mov r1, r13
    181         bl exc_dispatch
     181        bl ras_check
    182182        LOAD_REGS_FROM_STACK
    183183
    … …  
    187187        mov r0, #4
    188188        mov r1, r13
    189         bl exc_dispatch
     189        bl ras_check
    190190        LOAD_REGS_FROM_STACK
    191191
    … …  
    195195        mov r0, #2
    196196        mov r1, r13
    197         bl exc_dispatch
     197        bl ras_check
    198198        LOAD_REGS_FROM_STACK
    199199

  • kernel/arch/arm32/src/mm/as.c

    r743e17b r985e26d2  
    3636#include <arch/mm/as.h>
    3737#include <genarch/mm/as_pt.h>
     38#include <genarch/mm/page_pt.h>
    3839#include <genarch/mm/asid_fifo.h>
    3940#include <mm/as.h>
     41#include <mm/tlb.h>
    4042#include <arch.h>
    4143
    … …  
    4951}
    5052
     53void as_install_arch(as_t *as)
     54{
     55        tlb_invalidate_all();
     56}
     57
    5158/** @}
    5259 */

  • kernel/arch/arm32/src/userspace.c

    r743e17b r985e26d2  
    3535
    3636#include <userspace.h>
     37#include <arch/ras.h>
    3738
    3839/** Struct for holding all general purpose registers.
    … …  
    7475        ustate.r1 = 0;
    7576
     77        /* pass the RAS page address in %r2 */
     78        ustate.r2 = (uintptr_t) ras_page;
     79
    7680        /* clear other registers */
    77         ustate.r2 = ustate.r3  = ustate.r4  = ustate.r5 =
    78             ustate.r6  = ustate.r7  = ustate.r8  = ustate.r9 = ustate.r10 =
    79             ustate.r11 = ustate.r12 = ustate.lr = 0;
     81        ustate.r3  = ustate.r4  = ustate.r5 = ustate.r6 = ustate.r7 =
     82            ustate.r8 = ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 =
     83            ustate.lr = 0;
    8084
    8185        /* set user stack */

  • kernel/arch/ia32/Makefile.inc

    r743e17b r985e26d2  
    3434BFD = binary
    3535TARGET = i686-pc-linux-gnu
     36CLANG_ARCH = i386
    3637TOOLCHAIN_DIR = $(CROSS_PREFIX)/ia32
    3738
    … …  
    4344ICC_CFLAGS += $(CMN1)
    4445SUNCC_CFLAGS += $(CMN1)
     46CLANG_CFLAGS += $(CMN1)
    4547
    4648## Accepted CPUs
    … …  
    7173GCC_CFLAGS += $(CMN2)
    7274ICC_CFLAGS += $(CMN2)
     75CLANG_CFLAGS += $(CMN2)
    7376
    7477ARCH_SOURCES = \

  • kernel/arch/ia32/include/cpu.h

    r743e17b r985e26d2  
    5050#include <arch/pm.h>
    5151#include <arch/asm.h>
     52#include <arch/cpuid.h>
    5253
    5354typedef struct {
    … …  
    5657        unsigned int model;
    5758        unsigned int stepping;
     59        cpuid_feature_info fi;
     60
    5861        tss_t *tss;
    5962       

  • kernel/arch/ia32/include/cpuid.h

    r743e17b r985e26d2  
    6363
    6464struct __cpuid_feature_info {
    65         unsigned                        : 23;
     65        unsigned      : 11;
     66        unsigned sep  :  1;
     67        unsigned      : 11;
    6668        unsigned mmx  :  1;
    6769        unsigned fxsr :  1;

  • kernel/arch/ia32/include/mm/page.h

    r743e17b r985e26d2  
    146146#define PFERR_CODE_RSVD         (1 << 3)       
    147147
    148 static inline int get_pt_flags(pte_t *pt, size_t i)
     148/** Page Table Entry. */
     149typedef struct {
     150        unsigned present : 1;
     151        unsigned writeable : 1;
     152        unsigned uaccessible : 1;
     153        unsigned page_write_through : 1;
     154        unsigned page_cache_disable : 1;
     155        unsigned accessed : 1;
     156        unsigned dirty : 1;
     157        unsigned pat : 1;
     158        unsigned global : 1;
     159        unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
     160        unsigned avl : 2;
     161        unsigned frame_address : 20;
     162} __attribute__ ((packed)) pte_t;
     163
     164static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    149165{
    150166        pte_t *p = &pt[i];

  • kernel/arch/ia32/include/types.h

    r743e17b r985e26d2  
    8080#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8181
    82 /** Page Table Entry. */
    83 typedef struct {
    84         unsigned present : 1;
    85         unsigned writeable : 1;
    86         unsigned uaccessible : 1;
    87         unsigned page_write_through : 1;
    88         unsigned page_cache_disable : 1;
    89         unsigned accessed : 1;
    90         unsigned dirty : 1;
    91         unsigned pat : 1;
    92         unsigned global : 1;
    93         unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
    94         unsigned avl : 2;
    95         unsigned frame_address : 20;
    96 } __attribute__ ((packed)) pte_t;
    97 
    9882#endif
    9983

  • kernel/arch/ia32/src/boot/boot.S

    r743e17b r985e26d2  
    8585        pse_supported:
    8686       
    87         bt $(INTEL_SEP), %edx
    88         jc sep_supported
    89        
    90                 movl $sep_msg, %esi
    91                 jmp error_halt
    92        
    93         sep_supported:
    94 
    9587#include "vesa_prot.inc"
    9688
    … …  
    225217        .asciz "Page Size Extension not supported. System halted."
    226218
    227 sep_msg:
    228         .asciz "SYSENTER/SYSEXIT not supported. System halted."

  • kernel/arch/ia32/src/cpu/cpu.c

    r743e17b r985e26d2  
    9292void cpu_arch_init(void)
    9393{
    94         cpuid_feature_info fi;
    9594        cpuid_extended_feature_info efi;
    9695        cpu_info_t info;
    … …  
    102101        CPU->fpu_owner = NULL;
    103102       
    104         cpuid(1, &info);
     103        cpuid(INTEL_CPUID_STANDARD, &info);
    105104       
    106         fi.word = info.cpuid_edx;
     105        CPU->arch.fi.word = info.cpuid_edx;
    107106        efi.word = info.cpuid_ecx;
    108107       
    109         if (fi.bits.fxsr)
     108        if (CPU->arch.fi.bits.fxsr)
    110109                fpu_fxsr();
    111110        else
    112111                fpu_fsr();
    113112       
    114         if (fi.bits.sse) {
     113        if (CPU->arch.fi.bits.sse) {
    115114                asm volatile (
    116115                        "mov %%cr4, %[help]\n"
    … …  
    122121        }
    123122       
    124         /* Setup fast SYSENTER/SYSEXIT syscalls */
    125         syscall_setup_cpu();
     123        if (CPU->arch.fi.bits.sep) {
     124                /* Setup fast SYSENTER/SYSEXIT syscalls */
     125                syscall_setup_cpu();
     126        }
    126127}
    127128
    … …  
    132133        CPU->arch.vendor = VendorUnknown;
    133134        if (has_cpuid()) {
    134                 cpuid(0, &info);
     135                cpuid(INTEL_CPUID_LEVEL, &info);
    135136
    136137                /*
    … …  
    150151                        CPU->arch.vendor = VendorIntel;
    151152               
    152                 cpuid(1, &info);
     153                cpuid(INTEL_CPUID_STANDARD, &info);
    153154                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
    154155                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;

  • kernel/arch/ia32/src/ia32.c

    r743e17b r985e26d2  
    6868#include <sysinfo/sysinfo.h>
    6969#include <arch/boot/boot.h>
     70#include <memstr.h>
    7071
    7172#ifdef CONFIG_SMP
    … …  
    169170                        i8042_wire(i8042_instance, kbrd);
    170171                        trap_virtual_enable_irqs(1 << IRQ_KBD);
     172                        trap_virtual_enable_irqs(1 << IRQ_MOUSE);
    171173                }
    172174        }
    … …  
    176178         * self-sufficient.
    177179         */
    178         sysinfo_set_item_val("kbd", NULL, true);
    179         sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
    180         sysinfo_set_item_val("kbd.address.physical", NULL,
     180        sysinfo_set_item_val("i8042", NULL, true);
     181        sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD);
     182        sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE);
     183        sysinfo_set_item_val("i8042.address.physical", NULL,
    181184            (uintptr_t) I8042_BASE);
    182         sysinfo_set_item_val("kbd.address.kernel", NULL,
     185        sysinfo_set_item_val("i8042.address.kernel", NULL,
    183186            (uintptr_t) I8042_BASE);
    184187#endif

  • kernel/arch/ia32/src/interrupt.c

    r743e17b r985e26d2  
    9898}
    9999
     100static void de_fault(int n, istate_t *istate)
     101{
     102        fault_if_from_uspace(istate, "Divide error.");
     103
     104        decode_istate(istate);
     105        panic("Divide error.");
     106}
     107
    100108/** General Protection Fault. */
    101109static void gp_fault(int n __attribute__((unused)), istate_t *istate)
    … …  
    215223        }
    216224       
     225        exc_register(0, "de_fault", (iroutine) de_fault);
    217226        exc_register(7, "nm_fault", (iroutine) nm_fault);
    218227        exc_register(12, "ss_fault", (iroutine) ss_fault);

  • kernel/arch/ia32/src/proc/scheduler.c

    r743e17b r985e26d2  
    6161            SP_DELTA];
    6262       
    63         /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
    64         write_msr(IA32_MSR_SYSENTER_ESP, kstk);
     63        if (CPU->arch.fi.bits.sep) {
     64                /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
     65                write_msr(IA32_MSR_SYSENTER_ESP, kstk);
     66        }
    6567       
    6668        /* Set kernel stack for CPL3 -> CPL0 switch via interrupt */

  • kernel/arch/ia32/src/userspace.c

    r743e17b r985e26d2  
    7070                "movl %[uarg], %%eax\n"
    7171               
    72                 /* %ebx is defined to hold pcb_ptr - set it to 0 */
    73                 "xorl %%ebx, %%ebx\n"
     72                /* %edi is defined to hold pcb_ptr - set it to 0 */
     73                "xorl %%edi, %%edi\n"
    7474               
    7575                "iret\n"

  • kernel/arch/ia64/_link.ld.in

    r743e17b r985e26d2  
    77 */
    88
     9#define LOAD_ADDRESS_V  0xe000000004404000
     10#define LOAD_ADDRESS_P  0x0000000004404000
     11
    912ENTRY(kernel_image_start)
    1013
    1114SECTIONS {
    12         .image 0xe000000004404000: AT (0x0000000004404000) {
     15        .image LOAD_ADDRESS_V: AT (LOAD_ADDRESS_P) {
    1316                ktext_start = .;
    1417                *(K_TEXT_START);
    … …  
    2124                *(.opd)
    2225                *(.data .data.*)
     26                hardcoded_load_address = .;
     27                QUAD(LOAD_ADDRESS_V);
     28                hardcoded_ktext_size = .;
     29                QUAD(ktext_end - ktext_start);
     30                hardcoded_kdata_size = .;
     31                QUAD(kdata_end - kdata_start);
    2332                *(.got .got.*)
    2433                *(.sdata)
    … …  
    3847        }
    3948
    40         _hardcoded_ktext_size = ktext_end - ktext_start;
    41         _hardcoded_kdata_size = kdata_end - kdata_start;
    42         _hardcoded_load_address = 0xe000000004404000;
    43 
    4449}

  • kernel/arch/ia64/src/cpu/cpu.c

    r743e17b r985e26d2  
    3737#include <arch/register.h>
    3838#include <print.h>
     39#include <memstr.h>
    3940
    4041void cpu_arch_init(void)

  • kernel/arch/ia64/src/ivt.S

    r743e17b r985e26d2  
    391391
    392392    /* 10. call handler */
    393         movl r1 = _hardcoded_load_address
     393        movl r1 = kernel_image_start
    394394   
    395395        mov b1 = loc2

  • kernel/arch/ia64/src/start.S

    r743e17b r985e26d2  
    186186        movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
    187187        or r20 = r20, r1 ;;
    188         movl r1 = _hardcoded_load_address
     188        movl r1 = kernel_image_start
    189189       
    190190        /*
    191          * Initialize hardcoded_* variables. Do only BSP
     191         * Initialize bootinfo on BSP.
    192192         */
    193 (p3)    movl r14 = _hardcoded_ktext_size
    194 (p3)    movl r15 = _hardcoded_kdata_size
    195 (p3)    movl r16 = _hardcoded_load_address ;;
    196 (p3)    addl r17 = @gprel(hardcoded_ktext_size), gp
    197 (p3)    addl r18 = @gprel(hardcoded_kdata_size), gp
    198 (p3)    addl r19 = @gprel(hardcoded_load_address), gp
    199 (p3)    addl r21 = @gprel(bootinfo), gp
    200                 ;;
    201 (p3)    st8 [r17] = r14
    202 (p3)    st8 [r18] = r15
    203 (p3)    st8 [r19] = r16
     193(p3)    addl r21 = @gprel(bootinfo), gp ;;
    204194(p3)    st8 [r21] = r20
    205195       

  • kernel/arch/mips32/include/mm/page.h

    r743e17b r985e26d2  
    141141#include <arch/exception.h>
    142142
    143 static inline int get_pt_flags(pte_t *pt, size_t i)
     143/** Page Table Entry. */
     144typedef struct {
     145        unsigned g : 1;                 /**< Global bit. */
     146        unsigned p : 1;                 /**< Present bit. */
     147        unsigned d : 1;                 /**< Dirty bit. */
     148        unsigned cacheable : 1;         /**< Cacheable bit. */
     149        unsigned : 1;                   /**< Unused. */
     150        unsigned soft_valid : 1;        /**< Valid content even if not present. */
     151        unsigned pfn : 24;              /**< Physical frame number. */
     152        unsigned w : 1;                 /**< Page writable bit. */
     153        unsigned a : 1;                 /**< Accessed bit. */
     154} pte_t;
     155
     156
     157static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    144158{
    145159        pte_t *p = &pt[i];

  • kernel/arch/mips32/include/types.h

    r743e17b r985e26d2  
    8080#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8181
    82 /** Page Table Entry. */
    83 typedef struct {
    84         unsigned g : 1;                 /**< Global bit. */
    85         unsigned p : 1;                 /**< Present bit. */
    86         unsigned d : 1;                 /**< Dirty bit. */
    87         unsigned cacheable : 1;         /**< Cacheable bit. */
    88         unsigned : 1;                   /**< Unused. */
    89         unsigned soft_valid : 1;        /**< Valid content even if not present. */
    90         unsigned pfn : 24;              /**< Physical frame number. */
    91         unsigned w : 1;                 /**< Page writable bit. */
    92         unsigned a : 1;                 /**< Accessed bit. */
    93 } pte_t;
    94 
    9582#endif
    9683

  • kernel/arch/ppc32/include/mm/page.h

    r743e17b r985e26d2  
    131131#include <arch/interrupt.h>
    132132
    133 static inline int get_pt_flags(pte_t *pt, size_t i)
     133/** Page Table Entry. */
     134typedef struct {
     135        unsigned present : 1;             /**< Present bit. */
     136        unsigned page_write_through : 1;  /**< Write thought caching. */
     137        unsigned page_cache_disable : 1;  /**< No caching. */
     138        unsigned accessed : 1;            /**< Accessed bit. */
     139        unsigned global : 1;              /**< Global bit. */
     140        unsigned valid : 1;               /**< Valid content even if not present. */
     141        unsigned pfn : 20;                /**< Physical frame number. */
     142} pte_t;
     143
     144static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    134145{
    135146        pte_t *p = &pt[i];

  • kernel/arch/ppc32/include/types.h

    r743e17b r985e26d2  
    8282#define PRIxn "x"
    8383
    84 /** Page Table Entry. */
    85 typedef struct {
    86         unsigned present : 1;             /**< Present bit. */
    87         unsigned page_write_through : 1;  /**< Write thought caching. */
    88         unsigned page_cache_disable : 1;  /**< No caching. */
    89         unsigned accessed : 1;            /**< Accessed bit. */
    90         unsigned global : 1;              /**< Global bit. */
    91         unsigned valid : 1;               /**< Valid content even if not present. */
    92         unsigned pfn : 20;                /**< Physical frame number. */
    93 } pte_t;
    94 
    9584#endif
    9685

  • kernel/arch/ppc32/src/mm/as.c

    r743e17b r985e26d2  
    3535#include <arch/mm/as.h>
    3636#include <genarch/mm/as_pt.h>
     37#include <genarch/mm/page_pt.h>
    3738#include <genarch/mm/asid_fifo.h>
    3839#include <arch.h>

  • kernel/arch/ppc32/src/mm/tlb.c

    r743e17b r985e26d2  
    3838#include <interrupt.h>
    3939#include <mm/as.h>
     40#include <mm/page.h>
    4041#include <arch.h>
    4142#include <print.h>

  • kernel/arch/ppc32/src/ppc32.c

    r743e17b r985e26d2  
    4444#include <genarch/ofw/pci.h>
    4545#include <userspace.h>
     46#include <mm/page.h>
    4647#include <proc/uarg.h>
    4748#include <console/console.h>

  • kernel/arch/sparc64/src/context.S

    r743e17b r985e26d2  
    2828
    2929#include <arch/context_offset.h>
    30 
    31 /**
    32  * Both context_save_arch() and context_restore_arch() are
    33  * leaf-optimized procedures. This kind of optimization
    34  * is very important and prevents any implicit window
    35  * spill/fill/clean traps in these very core kernel
    36  * functions.
    37  */
    38        
    39 #include <arch/context_offset.h>
     30#include <arch/arch.h>
     31#include <arch/regdef.h>
    4032
    4133.text   
    … …  
    4436.global context_restore_arch
    4537
     38/*
     39 * context_save_arch() is required not to create its own stack frame. See the
     40 * generic context.h for explanation.
     41 */
    4642context_save_arch:
     43        #
     44        # Force all our active register windows to memory so that we can find
     45        # them there even if e.g. the thread is migrated to another processor.
     46        #
     47        flushw
     48
    4749        CONTEXT_SAVE_ARCH_CORE %o0
    4850        retl
    … …  
    5153context_restore_arch:
    5254        #
    53         # Flush all active windows.
    54         # This is essential, because CONTEXT_LOAD overwrites
    55         # %sp of CWP - 1 with the value written to %fp of CWP.
    56         # Flushing all active windows mitigates this problem
    57         # as CWP - 1 becomes the overlap window.
     55        # Forget all previous windows, they are not going to be needed again.
     56        # Enforce a window fill on the next RESTORE instruction by setting
     57        # CANRESTORE to zero and other window configuration registers
     58        # accordingly. Note that the same can be achieved by executing the
     59        # FLUSHW instruction, but since we don't need to remember the previous
     60        # windows, we do the former and save thus some unnecessary window
     61        # spills.
    5862        #
    59         flushw
    60        
     63        rdpr %pstate, %l0
     64        andn %l0, PSTATE_IE_BIT, %l1
     65        wrpr %l1, %pstate
     66        wrpr %g0, 0, %canrestore
     67        wrpr %g0, 0, %otherwin
     68        wrpr %g0, NWINDOWS - 2, %cansave
     69        wrpr %l0, %pstate
     70
    6171        CONTEXT_RESTORE_ARCH_CORE %o0
    6272        retl

  • kernel/arch/sparc64/src/mm/tlb.c

    r743e17b r985e26d2  
    3737#include <mm/as.h>
    3838#include <mm/asid.h>
     39#include <genarch/mm/page_ht.h>
    3940#include <arch/mm/frame.h>
    4041#include <arch/mm/page.h>

  • kernel/arch/sparc64/src/trap/trap_table.S

    r743e17b r985e26d2  
    652652         * spilled to kernel memory (i.e. register window buffer). Moreover,
    653653         * if the scheduler was called in the meantime, all valid windows
    654          * belonging to other threads were spilled by context_restore().
     654         * belonging to other threads were spilled by context_save().
    655655         * If OTHERWIN is non-zero, then some userspace windows are still
    656656         * valid. Others might have been spilled. However, the CWP pointer
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