Changeset 96e01fbc in mainline for uspace/lib/c/arch


Ignore:
Timestamp:
2012-08-31T17:30:29Z (13 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
2be2506a
Parents:
e0d5bc5 (diff), 0d57c3e (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
uspace/lib/c/arch
Files:
26 edited

Legend:

Unmodified
Added
Removed

  • uspace/lib/c/arch/abs32le/_link.ld.in

    re0d5bc5 r96e01fbc  
    1414SECTIONS {
    1515#ifdef LOADER
     16        . = 0x70001000 + SIZEOF_HEADERS;
     17       
    1618        .interp : {
    1719                *(.interp);
    18         } :interp
    19        
    20         . = 0x70001000 + SIZEOF_HEADERS;
     20        } :interp :text
    2121#else
    2222        . = 0x1000 + SIZEOF_HEADERS;
    2323#endif
     24       
     25        /* Make sure the code is aligned reasonably */
     26        . = ALIGN(., 16);
     27       
    2428        .text : {
    2529                *(.text .text.*);

  • uspace/lib/c/arch/abs32le/include/types.h

    re0d5bc5 r96e01fbc  
    4747
    4848typedef uint32_t sysarg_t;
     49typedef int32_t native_t;
    4950
    5051typedef int32_t ssize_t;

  • uspace/lib/c/arch/amd64/_link.ld.in

    re0d5bc5 r96e01fbc  
    1515SECTIONS {
    1616#ifdef LOADER
     17        . = 0x70001000 + SIZEOF_HEADERS;
     18       
    1719        .interp : {
    1820                *(.interp);
    19         } :interp
    20        
    21         . = 0x70001000 + SIZEOF_HEADERS;
     21        } :interp :text
    2222#else
    2323        . = 0x1000 + SIZEOF_HEADERS;
    2424#endif
     25       
     26        /* Make sure the code is aligned reasonably */
     27        . = ALIGN(., 16);
     28       
    2529        .init : {
    2630                *(.init);

  • uspace/lib/c/arch/amd64/include/elf_linux.h

    re0d5bc5 r96e01fbc  
    6666        uint64_t rsp;
    6767        uint64_t ss;
     68
     69        /*
     70         * The following registers need to be part of elf_regs_t.
     71         * Unfortunately, we don't have any information about them in our
     72         * istate_t.
     73         */
     74        uint64_t unused_fs_base;
     75        uint64_t unused_gs_base;
     76        uint64_t unused_ds;
     77        uint64_t unused_es;
     78        uint64_t unused_fs;
     79        uint64_t unused_gs;
    6880} elf_regs_t;
    6981
    … …  
    91103        elf_regs->rsp = istate->rsp;
    92104        elf_regs->ss = istate->ss;
     105
     106        /*
     107         * Reset the registers for which there is not enough info in istate_t.
     108         */
     109        elf_regs->unused_fs_base = 0;
     110        elf_regs->unused_gs_base = 0;
     111        elf_regs->unused_ds = 0;
     112        elf_regs->unused_es = 0;
     113        elf_regs->unused_fs = 0;
     114        elf_regs->unused_gs = 0;
    93115}
    94116

  • uspace/lib/c/arch/amd64/include/types.h

    re0d5bc5 r96e01fbc  
    4747
    4848typedef uint64_t sysarg_t;
     49typedef int64_t native_t;
    4950
    5051typedef int64_t ssize_t;

  • uspace/lib/c/arch/arm32/_link.ld.in

    re0d5bc5 r96e01fbc  
    1414SECTIONS {
    1515#ifdef LOADER
     16        . = 0x70001000 + SIZEOF_HEADERS;
     17       
    1618        .interp : {
    1719                *(.interp);
    18         } :interp
    19        
    20         . = 0x70001000 + SIZEOF_HEADERS;
     20        } :interp :text
    2121#else
    2222        . = 0x1000 + SIZEOF_HEADERS;
    2323#endif
     24       
     25        /* Make sure the code is aligned reasonably */
     26        . = ALIGN(., 8);
     27       
    2428        .init : {
    2529                *(.init);

  • uspace/lib/c/arch/arm32/include/types.h

    re0d5bc5 r96e01fbc  
    4848
    4949typedef uint32_t sysarg_t;
     50typedef int32_t native_t;
    5051
    5152typedef int32_t ssize_t;

  • uspace/lib/c/arch/arm32/src/fibril.S

    re0d5bc5 r96e01fbc  
    3535        stmia r0!, {sp, lr}
    3636        stmia r0!, {r4-r11}
    37 
     37       
    3838        # return 1
    3939        mov r0, #1
    … …  
    4343        ldmia r0!, {sp, lr}
    4444        ldmia r0!, {r4-r11}
    45 
    46         #return 0
     45       
     46        # return 0
    4747        mov r0, #0
    4848        mov pc, lr

  • uspace/lib/c/arch/arm32/src/stacktrace_asm.S

    re0d5bc5 r96e01fbc  
    4141
    4242stacktrace_pc_get:
    43         mov r0, lr 
     43        mov r0, lr
    4444        mov pc, lr

  • uspace/lib/c/arch/arm32/src/thread_entry.s

    re0d5bc5 r96e01fbc  
    4242        push {fp, ip, lr, pc}
    4343        sub fp, ip, #4
    44 
    45         b __thread_main
     44       
     45        b __thread_main

  • uspace/lib/c/arch/ia32/_link.ld.in

    re0d5bc5 r96e01fbc  
    1919
    2020SECTIONS {
    21 #if defined(LOADER) || defined(DLEXE)
    22         .interp : {
    23                 *(.interp);
    24         } :interp
    25 #endif
    2621#ifdef LOADER
    2722        . = 0x70001000 + SIZEOF_HEADERS;
    … …  
    2924        . = 0x1000 + SIZEOF_HEADERS;
    3025#endif
     26       
     27#if defined(LOADER) || defined(DLEXE)
     28        .interp : {
     29                *(.interp);
     30        } :interp :text
     31#endif
     32       
     33        /* Make sure the code is aligned reasonably */
     34        . = ALIGN(., 16);
     35       
    3136        .init : {
    3237                *(.init);
    … …  
    3742                *(.rodata .rodata.*);
    3843        } :text
    39 
     44       
    4045#if defined(SHLIB) || defined(DLEXE)
    4146        .rel.plt : {
    … …  
    8085#if defined(SHLIB) || defined(DLEXE)
    8186        .data.rel : {
    82                 *(.data.rel .data.rel.*);
     87                *(.data.rel .data.rel.*);
    8388        } :data
    84 
     89       
    8590        .got : {
    86                 *(.got);
     91                *(.got);
    8792        } :data
     93       
    8894        .got.plt : {
    89                 *(.got.plt);
     95                *(.got.plt);
    9096        } :data
    9197#endif

  • uspace/lib/c/arch/ia32/include/types.h

    re0d5bc5 r96e01fbc  
    4747
    4848typedef uint32_t sysarg_t;
     49typedef int32_t native_t;
    4950
    5051typedef int32_t ssize_t;

  • uspace/lib/c/arch/ia64/Makefile.common

    re0d5bc5 r96e01fbc  
    2727#
    2828
    29 GCC_CFLAGS += -fno-unwind-tables
     29#
     30# FIXME:
     31#
     32# The -fno-selective-scheduling and -fno-selective-scheduling2 options
     33# should be removed as soon as a bug in GCC concerning unchecked
     34# speculative loads is fixed.
     35#
     36# See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53975 for reference.
     37#
     38
     39GCC_CFLAGS += -fno-unwind-tables -fno-selective-scheduling -fno-selective-scheduling2
    3040
    3141ENDIANESS = LE

  • uspace/lib/c/arch/ia64/_link.ld.in

    re0d5bc5 r96e01fbc  
    1414SECTIONS {
    1515#ifdef LOADER
     16        . = 0x800000000 + SIZEOF_HEADERS;
     17       
    1618        .interp : {
    1719                *(.interp);
    18         } :interp
    19        
    20         . = 0x800000000 + SIZEOF_HEADERS;
     20        } :interp :text
    2121#else
    2222        . = 0x4000 + SIZEOF_HEADERS;
    2323#endif
    24         /*
    25          * XXX This is just a work around. Problem: .init section does not
    26          * have the proper alignment.
    27          */
     24       
     25        /* Make sure the code is aligned reasonably */
    2826        . = ALIGN(., 16);
    29 
     27       
    3028        .init : {
    3129                *(.init);

  • uspace/lib/c/arch/ia64/include/types.h

    re0d5bc5 r96e01fbc  
    5757
    5858typedef uint64_t sysarg_t;
     59typedef int64_t native_t;
    5960
    6061typedef int64_t ssize_t;

  • uspace/lib/c/arch/mips32/Makefile.common

    re0d5bc5 r96e01fbc  
    2727#
    2828
    29 GCC_CFLAGS += -mips3 -mabi=32
     29GCC_CFLAGS += -msoft-float -mips3 -mabi=32
    3030
    3131ENDIANESS = LE

  • uspace/lib/c/arch/mips32/_link.ld.in

    re0d5bc5 r96e01fbc  
    1414SECTIONS {
    1515#ifdef LOADER
     16        . = 0x70004000 + SIZEOF_HEADERS;
     17       
    1618        .interp : {
    1719                *(.interp);
    18         } :interp
    19        
    20         . = 0x70004000 + SIZEOF_HEADERS;
     20        } :interp :text
    2121#else
    2222        . = 0x4000 + SIZEOF_HEADERS;
    2323#endif
     24       
     25        /* Make sure the code is aligned reasonably */
     26        . = ALIGN(., 16);
     27       
    2428        .init : {
    2529                *(.init);

  • uspace/lib/c/arch/mips32/include/types.h

    re0d5bc5 r96e01fbc  
    4848
    4949typedef uint32_t sysarg_t;
     50typedef int32_t native_t;
    5051
    5152typedef int32_t ssize_t;

  • uspace/lib/c/arch/mips32eb/Makefile.common

    re0d5bc5 r96e01fbc  
    2727#
    2828
    29 GCC_CFLAGS += -mips3 -mabi=32
     29GCC_CFLAGS += -msoft-float -mips3 -mabi=32
    3030
    3131ENDIANESS = BE

  • uspace/lib/c/arch/mips64/Makefile.common

    re0d5bc5 r96e01fbc  
    2727#
    2828
    29 GCC_CFLAGS += -mips3 -mabi=64
     29GCC_CFLAGS += -msoft-float -mips3 -mabi=64
    3030AFLAGS = -64
    3131

  • uspace/lib/c/arch/mips64/_link.ld.in

    re0d5bc5 r96e01fbc  
    1515SECTIONS {
    1616#ifdef LOADER
     17        . = 0x70004000 + SIZEOF_HEADERS;
     18       
    1719        .interp : {
    1820                *(.interp);
    19         } :interp
    20        
    21         . = 0x70004000 + SIZEOF_HEADERS;
     21        } :interp :text
    2222#else
    2323        . = 0x4000 + SIZEOF_HEADERS;
    2424#endif
     25       
     26        /* Make sure the code is aligned reasonably */
     27        . = ALIGN(., 16);
     28       
    2529        .init : {
    2630                *(.init);

  • uspace/lib/c/arch/mips64/include/types.h

    re0d5bc5 r96e01fbc  
    4848
    4949typedef uint64_t sysarg_t;
     50typedef int64_t native_t;
    5051
    5152typedef int64_t ssize_t;

  • uspace/lib/c/arch/ppc32/_link.ld.in

    re0d5bc5 r96e01fbc  
    1515SECTIONS {
    1616#ifdef LOADER
     17        . = 0x70001000 + SIZEOF_HEADERS;
     18       
    1719        .interp : {
    1820                *(.interp);
    19         } :interp
    20        
    21         . = 0x70001000 + SIZEOF_HEADERS;
     21        } :interp :text
    2222#else
    2323        . = 0x1000 + SIZEOF_HEADERS;
    2424#endif
     25       
     26        /* Make sure the code is aligned reasonably */
     27        . = ALIGN(., 4);
     28       
    2529        .init : {
    2630                *(.init);

  • uspace/lib/c/arch/ppc32/include/types.h

    re0d5bc5 r96e01fbc  
    4747
    4848typedef uint32_t sysarg_t;
     49typedef int32_t native_t;
    4950
    5051typedef int32_t ssize_t;

  • uspace/lib/c/arch/sparc64/_link.ld.in

    re0d5bc5 r96e01fbc  
    1414SECTIONS {
    1515#ifdef LOADER
     16        . = 0x70004000 + SIZEOF_HEADERS;
     17       
    1618        .interp : {
    1719                *(.interp);
    18         } :interp
    19        
    20         . = 0x70004000 + SIZEOF_HEADERS;
     20        } :interp :text
    2121#else
    2222        . = 0x4000 + SIZEOF_HEADERS;
    2323#endif
     24       
     25        /* Make sure the code is aligned reasonably */
     26        . = ALIGN(., 16);
     27       
    2428        .init : {
    2529                *(.init);

  • uspace/lib/c/arch/sparc64/include/types.h

    re0d5bc5 r96e01fbc  
    4747
    4848typedef uint64_t sysarg_t;
     49typedef int64_t native_t;
    4950
    5051typedef int64_t ssize_t;
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