Index: kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c =================================================================== --- kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c (revision 0c2d9bb57bc590e00bd17e5f7cf0937be160cca7) +++ kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c (revision 96b972427511fafc3a7d22675c4ad68162b5f167) @@ -37,5 +37,4 @@ #include #include - #include Index: kernel/genarch/src/drivers/s3c24xx/irqc.c =================================================================== --- kernel/genarch/src/drivers/s3c24xx/irqc.c (revision 96b972427511fafc3a7d22675c4ad68162b5f167) +++ kernel/genarch/src/drivers/s3c24xx/irqc.c (revision 96b972427511fafc3a7d22675c4ad68162b5f167) @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2010 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Samsung S3C24xx on-chip interrupt controller. + * + * This IRQC is present on the Samsung S3C24xx CPU (on the gta02 platform). + */ + +#include +#include + +/** Correspondence between interrupt sources and sub-sources. */ +static unsigned s3c24xx_subsrc_src[][2] = { + { S3C24XX_SUBINT_CAM_P, S3C24XX_INT_CAM }, + { S3C24XX_SUBINT_CAM_C, S3C24XX_INT_CAM }, + { S3C24XX_SUBINT_ADC_S, S3C24XX_INT_ADC }, + { S3C24XX_SUBINT_TC, S3C24XX_INT_ADC }, + { S3C24XX_SUBINT_ERR2, S3C24XX_INT_UART2 }, + { S3C24XX_SUBINT_TXD2, S3C24XX_INT_UART2 }, + { S3C24XX_SUBINT_RXD2, S3C24XX_INT_UART2 }, + { S3C24XX_SUBINT_ERR1, S3C24XX_INT_UART1 }, + { S3C24XX_SUBINT_TXD1, S3C24XX_INT_UART1 }, + { S3C24XX_SUBINT_RXD1, S3C24XX_INT_UART1 }, + { S3C24XX_SUBINT_ERR0, S3C24XX_INT_UART0 }, + { S3C24XX_SUBINT_TXD0, S3C24XX_INT_UART0 }, + { S3C24XX_SUBINT_RXD0, S3C24XX_INT_UART0 } +}; + +/** Initialize S3C24xx interrupt controller. + * + * @param irqc Instance structure + * @param regs Register I/O structure + */ +void s3c24xx_irqc_init(s3c24xx_irqc_t *irqc, s3c24xx_irqc_regs_t *regs) +{ + irqc->regs = regs; + + /* Make all interrupt sources use IRQ mode (not FIQ). */ + pio_write_32(®s->intmod, 0x00000000); + + /* Disable all interrupt sources. */ + pio_write_32(®s->intmsk, 0xffffffff); + + /* Disable interrupts from all sub-sources. */ + pio_write_32(®s->intsubmsk, 0xffffffff); +} + +/** Obtain number of pending interrupt. */ +unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *irqc) +{ + return pio_read_32(&irqc->regs->intoffset); +} + +/** Clear pending interrupt condition including sub-sources. + * + * Clear source and interrupt pending condition and also automatically clear + * any sub-source pending condition pertaining to the source. + */ +void s3c24xx_irqc_clear(s3c24xx_irqc_t *irqc, unsigned inum) +{ + unsigned src, subsrc; + unsigned entries, i; + + entries = sizeof(s3c24xx_subsrc_src) / sizeof(s3c24xx_subsrc_src[0]); + + for (i = 0; i < entries; i++) { + subsrc = s3c24xx_subsrc_src[i][0]; + src = s3c24xx_subsrc_src[i][1]; + + if (src == inum) { + pio_write_32(&irqc->regs->subsrcpnd, + S3C24XX_SUBINT_BIT(subsrc)); + } + } + + pio_write_32(&irqc->regs->srcpnd, S3C24XX_INT_BIT(inum)); + pio_write_32(&irqc->regs->intpnd, S3C24XX_INT_BIT(inum)); +} + +/** Enable interrupts from the specified source. */ +void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *irqc, unsigned src) +{ + pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) & + ~S3C24XX_INT_BIT(src)); +} + +/** Disable interrupts from the specified source. */ +void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *irqc, unsigned src) +{ + pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) | + S3C24XX_INT_BIT(src)); +} + +/** Enable interrupts from the specified sub-source. */ +void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *irqc, unsigned subsrc) +{ + pio_write_32(&irqc->regs->intsubmsk, + pio_read_32(&irqc->regs->intsubmsk) & + ~S3C24XX_SUBINT_BIT(subsrc)); +} + +/** Disable interrupts from the specified sub-source. */ +void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *irqc, unsigned subsrc) +{ + pio_write_32(&irqc->regs->intsubmsk, + pio_read_32(&irqc->regs->intsubmsk) | + S3C24XX_SUBINT_BIT(subsrc)); +} + +/** @} + */ Index: kernel/genarch/src/drivers/s3c24xx/uart.c =================================================================== --- kernel/genarch/src/drivers/s3c24xx/uart.c (revision 96b972427511fafc3a7d22675c4ad68162b5f167) +++ kernel/genarch/src/drivers/s3c24xx/uart.c (revision 96b972427511fafc3a7d22675c4ad68162b5f167) @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2009 Martin Decky + * Copyright (c) 2010 Jiri Svoboda + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Samsung S3C24xx on-chip UART driver. + * + * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte) +{ + s3c24xx_uart_t *uart = + (s3c24xx_uart_t *) dev->data; + + /* Wait for space becoming available in Tx FIFO. */ + while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0) + ; + + pio_write_32(&uart->io->utxh, byte); +} + +static void s3c24xx_uart_putchar(outdev_t *dev, wchar_t ch) +{ + s3c24xx_uart_t *uart = + (s3c24xx_uart_t *) dev->data; + + if ((!uart->parea.mapped) || (console_override)) { + if (!ascii_check(ch)) { + s3c24xx_uart_sendb(dev, U_SPECIAL); + } else { + if (ch == '\n') + s3c24xx_uart_sendb(dev, (uint8_t) '\r'); + s3c24xx_uart_sendb(dev, (uint8_t) ch); + } + } +} + +static irq_ownership_t s3c24xx_uart_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void s3c24xx_uart_irq_handler(irq_t *irq) +{ + s3c24xx_uart_t *uart = irq->instance; + + while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) { + uint32_t data = pio_read_32(&uart->io->urxh); + pio_read_32(&uart->io->uerstat); + indev_push_character(uart->indev, data & 0xff); + } +} + +static outdev_operations_t s3c24xx_uart_ops = { + .write = s3c24xx_uart_putchar, + .redraw = NULL +}; + +outdev_t *s3c24xx_uart_init(uintptr_t paddr, inr_t inr) +{ + outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC); + if (!uart_dev) + return NULL; + + s3c24xx_uart_t *uart = + malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC); + if (!uart) { + free(uart_dev); + return NULL; + } + + outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops); + uart_dev->data = uart; + + uart->io = (s3c24xx_uart_io_t *) km_map(paddr, PAGE_SIZE, + PAGE_WRITE | PAGE_NOT_CACHEABLE); + uart->indev = NULL; + + /* Initialize IRQ structure. */ + irq_initialize(&uart->irq); + uart->irq.devno = device_assign_devno(); + uart->irq.inr = inr; + uart->irq.claim = s3c24xx_uart_claim; + uart->irq.handler = s3c24xx_uart_irq_handler; + uart->irq.instance = uart; + + /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ + pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE | + UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B); + + /* Set RX interrupt to pulse mode */ + pio_write_32(&uart->io->ucon, + pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL); + + link_initialize(&uart->parea.link); + uart->parea.pbase = paddr; + uart->parea.frames = 1; + uart->parea.unpriv = false; + uart->parea.mapped = false; + ddi_parea_register(&uart->parea); + + if (!fb_exported) { + /* + * This is the necessary evil until + * the userspace driver is entirely + * self-sufficient. + */ + sysinfo_set_item_val("fb", NULL, true); + sysinfo_set_item_val("fb.kind", NULL, 3); + sysinfo_set_item_val("fb.address.physical", NULL, paddr); + + fb_exported = true; + } + + return uart_dev; +} + +void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev) +{ + ASSERT(uart); + ASSERT(indev); + + uart->indev = indev; + irq_register(&uart->irq); +} + +/** @} + */ Index: kernel/genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c =================================================================== --- kernel/genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c (revision 0c2d9bb57bc590e00bd17e5f7cf0937be160cca7) +++ (revision ) @@ -1,141 +1,0 @@ -/* - * Copyright (c) 2010 Jiri Svoboda - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Samsung S3C24xx on-chip interrupt controller. - * - * This IRQC is present on the Samsung S3C24xx CPU (on the gta02 platform). - */ - -#include -#include - -/** Correspondence between interrupt sources and sub-sources. */ -static unsigned s3c24xx_subsrc_src[][2] = { - { S3C24XX_SUBINT_CAM_P, S3C24XX_INT_CAM }, - { S3C24XX_SUBINT_CAM_C, S3C24XX_INT_CAM }, - { S3C24XX_SUBINT_ADC_S, S3C24XX_INT_ADC }, - { S3C24XX_SUBINT_TC, S3C24XX_INT_ADC }, - { S3C24XX_SUBINT_ERR2, S3C24XX_INT_UART2 }, - { S3C24XX_SUBINT_TXD2, S3C24XX_INT_UART2 }, - { S3C24XX_SUBINT_RXD2, S3C24XX_INT_UART2 }, - { S3C24XX_SUBINT_ERR1, S3C24XX_INT_UART1 }, - { S3C24XX_SUBINT_TXD1, S3C24XX_INT_UART1 }, - { S3C24XX_SUBINT_RXD1, S3C24XX_INT_UART1 }, - { S3C24XX_SUBINT_ERR0, S3C24XX_INT_UART0 }, - { S3C24XX_SUBINT_TXD0, S3C24XX_INT_UART0 }, - { S3C24XX_SUBINT_RXD0, S3C24XX_INT_UART0 } -}; - -/** Initialize S3C24xx interrupt controller. - * - * @param irqc Instance structure - * @param regs Register I/O structure - */ -void s3c24xx_irqc_init(s3c24xx_irqc_t *irqc, s3c24xx_irqc_regs_t *regs) -{ - irqc->regs = regs; - - /* Make all interrupt sources use IRQ mode (not FIQ). */ - pio_write_32(®s->intmod, 0x00000000); - - /* Disable all interrupt sources. */ - pio_write_32(®s->intmsk, 0xffffffff); - - /* Disable interrupts from all sub-sources. */ - pio_write_32(®s->intsubmsk, 0xffffffff); -} - -/** Obtain number of pending interrupt. */ -unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *irqc) -{ - return pio_read_32(&irqc->regs->intoffset); -} - -/** Clear pending interrupt condition including sub-sources. - * - * Clear source and interrupt pending condition and also automatically clear - * any sub-source pending condition pertaining to the source. - */ -void s3c24xx_irqc_clear(s3c24xx_irqc_t *irqc, unsigned inum) -{ - unsigned src, subsrc; - unsigned entries, i; - - entries = sizeof(s3c24xx_subsrc_src) / sizeof(s3c24xx_subsrc_src[0]); - - for (i = 0; i < entries; i++) { - subsrc = s3c24xx_subsrc_src[i][0]; - src = s3c24xx_subsrc_src[i][1]; - - if (src == inum) { - pio_write_32(&irqc->regs->subsrcpnd, - S3C24XX_SUBINT_BIT(subsrc)); - } - } - - pio_write_32(&irqc->regs->srcpnd, S3C24XX_INT_BIT(inum)); - pio_write_32(&irqc->regs->intpnd, S3C24XX_INT_BIT(inum)); -} - -/** Enable interrupts from the specified source. */ -void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *irqc, unsigned src) -{ - pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) & - ~S3C24XX_INT_BIT(src)); -} - -/** Disable interrupts from the specified source. */ -void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *irqc, unsigned src) -{ - pio_write_32(&irqc->regs->intmsk, pio_read_32(&irqc->regs->intmsk) | - S3C24XX_INT_BIT(src)); -} - -/** Enable interrupts from the specified sub-source. */ -void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *irqc, unsigned subsrc) -{ - pio_write_32(&irqc->regs->intsubmsk, - pio_read_32(&irqc->regs->intsubmsk) & - ~S3C24XX_SUBINT_BIT(subsrc)); -} - -/** Disable interrupts from the specified sub-source. */ -void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *irqc, unsigned subsrc) -{ - pio_write_32(&irqc->regs->intsubmsk, - pio_read_32(&irqc->regs->intsubmsk) | - S3C24XX_SUBINT_BIT(subsrc)); -} - -/** @} - */ Index: kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c =================================================================== --- kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c (revision 0c2d9bb57bc590e00bd17e5f7cf0937be160cca7) +++ (revision ) @@ -1,169 +1,0 @@ -/* - * Copyright (c) 2009 Martin Decky - * Copyright (c) 2010 Jiri Svoboda - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Samsung S3C24xx on-chip UART driver. - * - * This UART is present on the Samsung S3C24xx CPU (on the gta02 platform). - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte) -{ - s3c24xx_uart_t *uart = - (s3c24xx_uart_t *) dev->data; - - /* Wait for space becoming available in Tx FIFO. */ - while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0) - ; - - pio_write_32(&uart->io->utxh, byte); -} - -static void s3c24xx_uart_putchar(outdev_t *dev, wchar_t ch) -{ - s3c24xx_uart_t *uart = - (s3c24xx_uart_t *) dev->data; - - if ((!uart->parea.mapped) || (console_override)) { - if (!ascii_check(ch)) { - s3c24xx_uart_sendb(dev, U_SPECIAL); - } else { - if (ch == '\n') - s3c24xx_uart_sendb(dev, (uint8_t) '\r'); - s3c24xx_uart_sendb(dev, (uint8_t) ch); - } - } -} - -static irq_ownership_t s3c24xx_uart_claim(irq_t *irq) -{ - return IRQ_ACCEPT; -} - -static void s3c24xx_uart_irq_handler(irq_t *irq) -{ - s3c24xx_uart_t *uart = irq->instance; - - while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) { - uint32_t data = pio_read_32(&uart->io->urxh); - pio_read_32(&uart->io->uerstat); - indev_push_character(uart->indev, data & 0xff); - } -} - -static outdev_operations_t s3c24xx_uart_ops = { - .write = s3c24xx_uart_putchar, - .redraw = NULL -}; - -outdev_t *s3c24xx_uart_init(uintptr_t paddr, inr_t inr) -{ - outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC); - if (!uart_dev) - return NULL; - - s3c24xx_uart_t *uart = - malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC); - if (!uart) { - free(uart_dev); - return NULL; - } - - outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops); - uart_dev->data = uart; - - uart->io = (s3c24xx_uart_io_t *) km_map(paddr, PAGE_SIZE, - PAGE_WRITE | PAGE_NOT_CACHEABLE); - uart->indev = NULL; - - /* Initialize IRQ structure. */ - irq_initialize(&uart->irq); - uart->irq.devno = device_assign_devno(); - uart->irq.inr = inr; - uart->irq.claim = s3c24xx_uart_claim; - uart->irq.handler = s3c24xx_uart_irq_handler; - uart->irq.instance = uart; - - /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ - pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE | - UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B); - - /* Set RX interrupt to pulse mode */ - pio_write_32(&uart->io->ucon, - pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL); - - link_initialize(&uart->parea.link); - uart->parea.pbase = paddr; - uart->parea.frames = 1; - uart->parea.unpriv = false; - uart->parea.mapped = false; - ddi_parea_register(&uart->parea); - - if (!fb_exported) { - /* - * This is the necessary evil until - * the userspace driver is entirely - * self-sufficient. - */ - sysinfo_set_item_val("fb", NULL, true); - sysinfo_set_item_val("fb.kind", NULL, 3); - sysinfo_set_item_val("fb.address.physical", NULL, paddr); - - fb_exported = true; - } - - return uart_dev; -} - -void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev) -{ - ASSERT(uart); - ASSERT(indev); - - uart->indev = indev; - irq_register(&uart->irq); -} - -/** @} - */