Changeset 93d66ef in mainline for kernel/arch/ia64

Timestamp:

2009-09-04T18:07:09Z (16 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

40240b1

Parents:

5bda2f3e

Message:

GCC 4.4.1 with -O3 uses speculative memory access
add basic support for deffering TLB faults on speculative access
this makes ia64 port work in Ski again (fixes ticket #115)

Location:

kernel/arch/ia64/src

Files:

• mm/tlb.c (modified) (1 diff)
• start.S (modified) (1 diff)

kernel/arch/ia64/src/mm/tlb.c

@@ -573 +573 @@
 void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
 {
+        if (istate->cr_isr.sp) {
+                /* Speculative load. Deffer the exception
+                   until a more clever approach can be used.
+                   
+                   Currently if we try to find the mapping
+                   for the speculative load while in the kernel,
+                   we might introduce a livelock because of
+                   the possibly invalid values of the address. */
+                istate->cr_ipsr.ed = true;
+                return;
+        }
+        
         uintptr_t va = istate->cr_ifa;  /* faulting address */
         

kernel/arch/ia64/src/start.S

@@ -125 +125 @@
         movl r10 = (KERNEL_TRANSLATION_FW)
         itr.d dtr[r7] = r10
+        
+        # Initialize DSR
+        
+        movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
+        mov r9 = cr.dcr
+        or r10 = r10, r9
+        mov cr.dcr = r10
         
         # Initialize PSR