Changeset 92778f2 in mainline for kernel/arch/sparc64/src

Timestamp:

2006-12-04T21:14:07Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4b43f86

Parents:

3d76996

Message:

Initial support for handling illegal virtual aliases on sparc64.

Location:

kernel/arch/sparc64/src

Files:

• cpu/cpu.c (modified) (1 diff)
• mm/as.c (modified) (3 diffs)
• mm/cache.c (added)
• mm/cache_asm.S (moved) (moved from kernel/arch/sparc64/src/mm/cache.S )
• mm/tlb.c (modified) (3 diffs)
• mm/tsb.c (modified) (2 diffs)
• smp/ipi.c (modified) (2 diffs)
• start.S (modified) (2 diffs)
• trap/interrupt.c (modified) (2 diffs)

kernel/arch/sparc64/src/cpu/cpu.c

@@ -93 +93 @@
         }
 
+        /*
+         * Set the D-cache active flag.
+         * Needed for the D-cache to work.
+         */
+        CPU->arch.dcache_active = 1;
 }
 

kernel/arch/sparc64/src/mm/as.c

@@ -48 +48 @@
 #include <bitops.h>
 #include <macros.h>
-#endif
+#endif /* CONFIG_TSB */
+
+#ifdef CONFIG_VIRT_IDX_DCACHE
+#include <arch/mm/cache.h>
+#endif /* CONFIG_VIRT_IDX_DCACHE */
 
 /** Architecture dependent address space init. */
@@ -159 +163 @@
         dtsb_base_write(tsb_base.value);
 #endif
+#ifdef CONFIG_VIRT_IDX_DCACHE
+        if (as->dcache_flush_on_install) {
+                /*
+                 * Some mappings in this address space are illegal address
+                 * aliases. Upon their creation, the flush_dcache_on_install
+                 * flag was set.
+                 *
+                 * We are now obliged to flush the D-cache in order to guarantee
+                 * that there will be at most one cache line for each address
+                 * alias.
+                 *
+                 * This flush performs a cleanup after another address space in
+                 * which the alias might have existed.
+                 */
+                dcache_flush();
+        }
+#endif /* CONFIG_VIRT_IDX_DCACHE */
 }
 
@@ -193 +214 @@
         }
 #endif
+#ifdef CONFIG_VIRT_IDX_DCACHE
+        if (as->dcache_flush_on_deinstall) {
+                /*
+                 * Some mappings in this address space are illegal address
+                 * aliases. Upon their creation, the flush_dcache_on_deinstall
+                 * flag was set.
+                 *
+                 * We are now obliged to flush the D-cache in order to guarantee
+                 * that there will be at most one cache line for each address
+                 * alias.
+                 *
+                 * This flush performs a cleanup after this address space. It is
+                 * necessary because other address spaces that contain the same
+                 * alias are not necessarily aware of the need to carry out the
+                 * cache flush. The only address spaces that are aware of it are
+                 * those that created the illegal alias. 
+                 */
+                dcache_flush();
+        }
+#endif /* CONFIG_VIRT_IDX_DCACHE */
 }
 

kernel/arch/sparc64/src/mm/tlb.c

@@ -112 +112 @@
         data.l = locked;
         data.cp = cacheable;
-#ifdef CONFIG_VIRT_IDX_CACHE
+#ifdef CONFIG_VIRT_IDX_DCACHE
         data.cv = cacheable;
-#endif /* CONFIG_VIRT_IDX_CACHE */
+#endif /* CONFIG_VIRT_IDX_DCACHE */
         data.p = true;
         data.w = true;
@@ -149 +149 @@
         data.l = false;
         data.cp = t->c;
-#ifdef CONFIG_VIRT_IDX_CACHE
+#ifdef CONFIG_VIRT_IDX_DCACHE
         data.cv = t->c;
-#endif /* CONFIG_VIRT_IDX_CACHE */
+#endif /* CONFIG_VIRT_IDX_DCACHE */
         data.p = t->k;          /* p like privileged */
         data.w = ro ? false : t->w;
@@ -185 +185 @@
         data.l = false;
         data.cp = t->c;
-#ifdef CONFIG_VIRT_IDX_CACHE
-        data.cv = t->c;
-#endif /* CONFIG_VIRT_IDX_CACHE */
         data.p = t->k;          /* p like privileged */
         data.w = false;

kernel/arch/sparc64/src/mm/tsb.c

@@ -101 +101 @@
         tsb->data.pfn = t->frame >> FRAME_WIDTH;
         tsb->data.cp = t->c;
-#ifdef CONFIG_VIRT_IDX_CACHE
-        tsb->data.cv = t->c;
-#endif /* CONFIG_VIRT_IDX_CACHE */
         tsb->data.p = t->k;             /* p as privileged */
         tsb->data.v = t->p;
@@ -143 +140 @@
         tsb->data.pfn = t->frame >> FRAME_WIDTH;
         tsb->data.cp = t->c;
-#ifdef CONFIG_VIRT_IDX_CACHE
+#ifdef CONFIG_VIRT_IDX_DCACHE
         tsb->data.cv = t->c;
-#endif /* CONFIG_VIRT_IDX_CACHE */
+#endif /* CONFIG_VIRT_IDX_DCACHE */
         tsb->data.p = t->k;             /* p as privileged */
         tsb->data.w = ro ? false : t->w;

kernel/arch/sparc64/src/smp/ipi.c

@@ -39 +39 @@
 #include <config.h>
 #include <mm/tlb.h>
+#include <arch/mm/cache.h>
 #include <arch/interrupt.h>
 #include <arch/trap/interrupt.h>
@@ -121 +122 @@
                 func = tlb_shootdown_ipi_recv;
                 break;
+        case IPI_DCACHE_SHOOTDOWN:
+                func = dcache_shootdown_ipi_recv;
+                break;
         default:
                 panic("Unknown IPI (%d).\n", ipi);

kernel/arch/sparc64/src/start.S

@@ -123 +123 @@
         membar #Sync
 
-#ifdef CONFIG_VIRT_IDX_CACHE
+#ifdef CONFIG_VIRT_IDX_DCACHE
 #define TTE_LOW_DATA(imm)       (TTE_CP | TTE_CV | TTE_P | LMA | (imm))
-#else /* CONFIG_VIRT_IDX_CACHE */
+#else /* CONFIG_VIRT_IDX_DCACHE */
 #define TTE_LOW_DATA(imm)       (TTE_CP | TTE_P | LMA | (imm))
-#endif /* CONFIG_VIRT_IDX_CACHE */
+#endif /* CONFIG_VIRT_IDX_DCACHE */
 
 #define SET_TLB_DATA(r1, r2, imm) \
@@ -361 +361 @@
 .global kernel_8k_tlb_data_template
 kernel_8k_tlb_data_template:
-#ifdef CONFIG_VIRT_IDX_CACHE
+#ifdef CONFIG_VIRT_IDX_DCACHE
         .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_CV | TTE_P | TTE_W)
-#else /* CONFIG_VIRT_IDX_CACHE */
+#else /* CONFIG_VIRT_IDX_DCACHE */
         .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_P | TTE_W)
-#endif /* CONFIG_VIRT_IDX_CACHE */
+#endif /* CONFIG_VIRT_IDX_DCACHE */

kernel/arch/sparc64/src/trap/interrupt.c

@@ -45 +45 @@
 #include <arch.h>
 #include <mm/tlb.h>
+#include <arch/mm/cache.h>
 #include <config.h>
 #include <synch/spinlock.h>
@@ -91 +92 @@
                 if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) {
                         tlb_shootdown_ipi_recv();
+                } else if (data0 == (uintptr_t) dcache_shootdown_ipi_recv) {
+                        dcache_shootdown_ipi_recv();
                 }
 #endif