Changeset 909c6e3 in mainline for arch/mips/src
- Timestamp:
- 2005-09-07T09:44:30Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- d246e7e
- Parents:
- 24bd23a
- Location:
- arch/mips/src
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips/src/context.S
r24bd23a r909c6e3 29 29 #define __ASM__ 30 30 #include <arch/asm/regname.h> 31 #include "context_offset.h"31 #include <arch/context_offset.h> 32 32 33 33 .text -
arch/mips/src/exception.c
r24bd23a r909c6e3 35 35 #include <debug.h> 36 36 37 void exception( void)37 void exception(struct exception_regdump *pstate) 38 38 { 39 39 int excno; 40 __u32 epc;41 40 __u32 epc_shift = 0; 42 41 … … 46 45 * NOTE ON OPERATION ORDERING 47 46 * 48 * On entry, cpu_priority_high() must be called before exception bit is cleared.49 * On exit, exception bit must be set before cpu_priority_restore() is called.47 * On entry, cpu_priority_high() must be called before 48 * exception bit is cleared. 50 49 */ 51 50 52 51 cpu_priority_high(); 53 epc = cp0_epc_read();54 52 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | 55 53 cp0_status_um_bit)); 56 54 57 if (THREAD) {58 THREAD->saved_epc = epc;59 }60 55 /* decode exception number and process the exception */ 61 56 switch (excno = (cp0_cause_read() >> 2) & 0x1f) { … … 65 60 case EXC_TLBL: 66 61 case EXC_TLBS: 67 tlb_invalid( );62 tlb_invalid(pstate); 68 63 break; 69 64 case EXC_Mod: … … 115 110 } 116 111 117 if (THREAD) 118 epc = THREAD->saved_epc; 119 120 /* Raise EXL bit before epc_write, so that we support 121 * properly nested exceptions 122 */ 123 cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit); 124 cp0_epc_write(epc + epc_shift); 112 pstate->epc += epc_shift; 125 113 } -
arch/mips/src/mm/tlb.c
r24bd23a r909c6e3 36 36 #include <symtab.h> 37 37 38 void tlb_refill( void)38 void tlb_refill(struct exception_regdump *pstate) 39 39 { 40 40 panic("tlb_refill exception\n"); 41 41 } 42 42 43 void tlb_invalid( void)43 void tlb_invalid(struct exception_regdump *pstate) 44 44 { 45 45 char *symbol = ""; 46 46 47 47 if (THREAD) { 48 char *s = get_symtab_entry( THREAD->saved_epc);48 char *s = get_symtab_entry(pstate->epc); 49 49 if (s) 50 50 symbol = s; 51 51 } 52 52 panic("%X: TLB exception at %X(%s)\n", cp0_badvaddr_read(), 53 THREAD ? THREAD->saved_epc : 0, symbol);53 pstate->epc, symbol); 54 54 } 55 55 -
arch/mips/src/start.S
r24bd23a r909c6e3 32 32 #include <arch/mm/page.h> 33 33 #include <arch/asm/boot.h> 34 #include <arch/context .h>34 #include <arch/context_offset.h> 35 35 36 36 .text … … 56 56 sw $a2,EOFFSET_A2(\r) 57 57 sw $a3,EOFFSET_A3(\r) 58 sw $t0,EOFFSET_ A4(\r)58 sw $t0,EOFFSET_T0(\r) 59 59 sw $t1,EOFFSET_T1(\r) 60 60 sw $t2,EOFFSET_T2(\r) … … 87 87 mfc0 $at, $status 88 88 sw $at,EOFFSET_STATUS(\r) 89 mfc0 $at, $epc 90 sw $at,EOFFSET_EPC(\r) 89 91 .endm 90 92 … … 96 98 lw $a2,EOFFSET_A2(\r) 97 99 lw $a3,EOFFSET_A3(\r) 98 lw $t0,EOFFSET_ A4(\r)100 lw $t0,EOFFSET_T0(\r) 99 101 lw $t1,EOFFSET_T1(\r) 100 102 lw $t2,EOFFSET_T2(\r) … … 125 127 lw $at,EOFFSET_STATUS(\r) 126 128 mtc0 $at, $status 129 lw $at,EOFFSET_EPC(\r) 130 mtc0 $at, $epc 127 131 128 132 lw $at,EOFFSET_AT(\r) … … 192 196 add $sp, $k0, 0 193 197 194 jal exception 198 add $a0, $sp, 0 199 jal exception /* exception(register_space) */ 195 200 nop 196 201 … … 206 211 add $sp, $k0, 0 207 212 208 jal tlb_refill 213 add $a0, $sp, 0 214 jal tlb_refill /* tlb_refill(register_space) */ 209 215 nop 210 216
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