Changeset 909c6e3 in mainline for arch/mips/src


Ignore:
Timestamp:
2005-09-07T09:44:30Z (20 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d246e7e
Parents:
24bd23a
Message:

MIPS exception now saves all necesssary information only on stack.

Location:
arch/mips/src
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • arch/mips/src/context.S

    r24bd23a r909c6e3  
    2929#define __ASM__
    3030#include <arch/asm/regname.h>
    31 #include "context_offset.h"
     31#include <arch/context_offset.h>
    3232       
    3333.text   
  • arch/mips/src/exception.c

    r24bd23a r909c6e3  
    3535#include <debug.h>
    3636
    37 void exception(void)
     37void exception(struct exception_regdump *pstate)
    3838{
    3939        int excno;
    40         __u32 epc;
    4140        __u32 epc_shift = 0;
    4241
     
    4645         * NOTE ON OPERATION ORDERING
    4746         *
    48          * On entry, cpu_priority_high() must be called before exception bit is cleared.
    49          * On exit, exception bit must be set before cpu_priority_restore() is called.
     47         * On entry, cpu_priority_high() must be called before
     48         * exception bit is cleared.
    5049         */
    5150
    5251        cpu_priority_high();
    53         epc = cp0_epc_read();
    5452        cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
    5553                                                cp0_status_um_bit));
    5654
    57         if (THREAD) {
    58                 THREAD->saved_epc = epc;
    59         }
    6055        /* decode exception number and process the exception */
    6156        switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
     
    6560                case EXC_TLBL:
    6661                case EXC_TLBS:
    67                         tlb_invalid();
     62                        tlb_invalid(pstate);
    6863                        break;
    6964                case EXC_Mod:
     
    115110        }
    116111       
    117         if (THREAD)
    118                 epc = THREAD->saved_epc;
    119        
    120         /* Raise EXL bit before epc_write, so that we support
    121          * properly nested exceptions
    122          */
    123         cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit);
    124         cp0_epc_write(epc + epc_shift);
     112        pstate->epc += epc_shift;
    125113}
  • arch/mips/src/mm/tlb.c

    r24bd23a r909c6e3  
    3636#include <symtab.h>
    3737
    38 void tlb_refill(void)
     38void tlb_refill(struct exception_regdump *pstate)
    3939{
    4040        panic("tlb_refill exception\n");
    4141}
    4242
    43 void tlb_invalid(void)
     43void tlb_invalid(struct exception_regdump *pstate)
    4444{
    4545        char *symbol = "";
    4646
    4747        if (THREAD) {
    48                 char *s = get_symtab_entry(THREAD->saved_epc);
     48                char *s = get_symtab_entry(pstate->epc);
    4949                if (s)
    5050                        symbol = s;
    5151        }
    5252        panic("%X: TLB exception at %X(%s)\n", cp0_badvaddr_read(),
    53               THREAD ? THREAD->saved_epc : 0, symbol);
     53              pstate->epc, symbol);
    5454}
    5555
  • arch/mips/src/start.S

    r24bd23a r909c6e3  
    3232#include <arch/mm/page.h>
    3333#include <arch/asm/boot.h>
    34 #include <arch/context.h>
     34#include <arch/context_offset.h>
    3535       
    3636.text
     
    5656        sw $a2,EOFFSET_A2(\r)
    5757        sw $a3,EOFFSET_A3(\r)
    58         sw $t0,EOFFSET_A4(\r)
     58        sw $t0,EOFFSET_T0(\r)
    5959        sw $t1,EOFFSET_T1(\r)
    6060        sw $t2,EOFFSET_T2(\r)
     
    8787        mfc0 $at, $status
    8888        sw $at,EOFFSET_STATUS(\r)
     89        mfc0 $at, $epc
     90        sw $at,EOFFSET_EPC(\r)
    8991.endm
    9092
     
    9698        lw $a2,EOFFSET_A2(\r)
    9799        lw $a3,EOFFSET_A3(\r)
    98         lw $t0,EOFFSET_A4(\r)
     100        lw $t0,EOFFSET_T0(\r)
    99101        lw $t1,EOFFSET_T1(\r)
    100102        lw $t2,EOFFSET_T2(\r)
     
    125127        lw $at,EOFFSET_STATUS(\r)
    126128        mtc0 $at, $status
     129        lw $at,EOFFSET_EPC(\r)
     130        mtc0 $at, $epc
    127131       
    128132        lw $at,EOFFSET_AT(\r)
     
    192196        add $sp, $k0, 0
    193197
    194         jal exception
     198        add $a0, $sp, 0
     199        jal exception /* exception(register_space) */
    195200        nop
    196201
     
    206211        add $sp, $k0, 0
    207212
    208         jal tlb_refill
     213        add $a0, $sp, 0
     214        jal tlb_refill /* tlb_refill(register_space) */
    209215        nop
    210216
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