Changeset 904b1bc in mainline for uspace/drv/bus/usb


Ignore:
Timestamp:
2018-05-22T10:36:58Z (7 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a4eb3ba2
Parents:
4f8772d4
git-author:
Jiri Svoboda <jiri@…> (2018-05-21 17:36:30)
git-committer:
Jiri Svoboda <jiri@…> (2018-05-22 10:36:58)
Message:

Fix remaining ccheck issues.

Location:
uspace/drv/bus/usb
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h

    r4f8772d4 r904b1bc  
    4343
    4444        volatile uint32_t transaction[8];
     45        volatile uint32_t buffer_pointer[7];
     46
     47        /* 64 bit struct only */
     48        volatile uint32_t extended_bp[7];
     49} __attribute__((packed, aligned(32))) itd_t;
     50
     51/*
     52 * itd_t.transaction
     53 */
    4554#define ITD_TRANSACTION_STATUS_ACTIVE_FLAG  (1 << 31)
    4655#define ITD_TRANSACTION_STATUS_BUFFER_ERROR_FLAG  (1 << 30)
    … …  
    5564#define ITD_TRANSACTION_OFFSET_SHIFT   0
    5665
    57         volatile uint32_t buffer_pointer[7];
     66/*
     67 * itd_t.buffer_pointer
     68 */
    5869#define ITD_BUFFER_POINTER_MASK      0xfffff000
    5970/* First buffer pointer */
    … …  
    7081#define ITD_BUFFER_POINTER_MULTI_SHIFT   0
    7182
    72         /* 64 bit struct only */
    73         volatile uint32_t extended_bp[7];
    74 } __attribute__((packed, aligned(32))) itd_t;
    7583#endif
     84
    7685/**
    7786 * @}

  • uspace/drv/bus/usb/ehci/hw_struct/queue_head.h

    r4f8772d4 r904b1bc  
    4949
    5050        volatile uint32_t ep_char;
     51        volatile uint32_t ep_cap;
     52
     53        link_pointer_t current;
     54        /* Transfer overlay starts here */
     55        link_pointer_t next;
     56        link_pointer_t alternate;
     57        volatile uint32_t status;
     58        volatile uint32_t buffer_pointer[5];
     59
     60        /* 64 bit struct only */
     61        volatile uint32_t extended_bp[5];
     62} __attribute__((packed, aligned(32))) qh_t;
     63
     64/*
     65 * qh_t.ep_char
     66 */
    5167#define QH_EP_CHAR_RL_MASK    0xf
    5268#define QH_EP_CHAR_RL_SHIFT   28
    … …  
    7894    (((val) >> QH_EP_CHAR_ADDR_SHIFT) & QH_EP_CHAR_ADDR_MASK)
    7995
    80         volatile uint32_t ep_cap;
     96/*
     97 * qh_t.ep_cap
     98 */
    8199#define QH_EP_CAP_MULTI_MASK   0x3
    82100#define QH_EP_CAP_MULTI_SHIFT  30
    … …  
    100118        (((val) & QH_EP_CAP_S_MASK_MASK) << QH_EP_CAP_S_MASK_SHIFT)
    101119
    102         link_pointer_t current;
    103 /* Transfer overlay starts here */
    104         link_pointer_t next;
    105         link_pointer_t alternate;
     120/*
     121 * qh_t.alternate
     122 */
    106123#define QH_ALTERNATE_NACK_CNT_MASK   0x7
    107124#define QH_ALTERNATE_NACK_CNT_SHIFT  1
    108125
    109         volatile uint32_t status;
     126/*
     127 * qh_t.status
     128 */
    110129#define QH_STATUS_TOGGLE_FLAG   (1 << 31)
    111130#define QH_STATUS_TOTAL_MASK    0x7fff
    … …  
    127146#define QH_STATUS_PING_FLAG     (1 << 0)
    128147
    129         volatile uint32_t buffer_pointer[5];
     148/*
     149 * qh_t.buffer_pointer
     150 */
    130151#define QH_BUFFER_POINTER_MASK   0xfffff000
    131152/* Only the first buffer pointer */
    … …  
    141162#define QH_BUFFER_POINTER_FTAG_SHIFT  0
    142163
    143         /* 64 bit struct only */
    144         volatile uint32_t extended_bp[5];
    145 } __attribute__((packed, aligned(32))) qh_t;
    146164
    147165static inline void qh_append_qh(qh_t *qh, const qh_t *next)
    … …  
    212230}
    213231
    214 
    215 void qh_init(qh_t *instance, const endpoint_t *ep);
     232extern void qh_init(qh_t *instance, const endpoint_t *ep);
     233
    216234#endif
    217235/**

  • uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h

    r4f8772d4 r904b1bc  
    4343
    4444        volatile uint32_t ep;
     45        volatile uint32_t uframe;
     46        volatile uint32_t status;
     47        volatile uint32_t buffer_pointer[2];
     48        link_pointer_t back;
     49
     50        /* 64 bit struct only */
     51        volatile uint32_t extended_bp[2];
     52} __attribute__((packed, aligned(32))) sitd_t;
     53
     54/*
     55 * sitd_t.ep
     56 */
    4557#define SITD_EP_IN_FLAG         (1 << 31)
    4658#define SITD_EP_PORT_MASK       0x3f
    … …  
    5365#define SITD_EP_ADDR_SHIFT      0
    5466
    55         volatile uint32_t uframe;
     67/*
     68 * sitd_t.uframe
     69 */
    5670#define SITD_uFRAME_CMASK_MASK    0xff
    5771#define SITD_uFRAME_CMASK_SHIFT   8
    … …  
    5973#define SITD_uFRAME_SMASK_SHIFT   0
    6074
    61         volatile uint32_t status;
     75/*
     76 * sitd_t.status
     77 */
    6278#define SITD_STATUS_IOC_FLAG            (1 << 31)
    6379#define SITD_STATUS_PAGE_FLAG           (1 << 30)
    … …  
    7490#define SITD_STATUS_SPLIT_COMPLETE_FLAG (1 << 1)
    7591
    76         volatile uint32_t buffer_pointer[2];
     92/*
     93 * sitd_t.buffer_pointer
     94 */
    7795#define SITD_BUFFER_POINTER_MASK   0xfffff000
    7896/* Only the first page pointer */
    … …  
    85103#define SITD_BUFFER_POINTER_COUNT_SHIFT   0
    86104
    87         link_pointer_t back;
     105#endif
    88106
    89         /* 64 bit struct only */
    90         volatile uint32_t extended_bp[2];
    91 } __attribute__((packed, aligned(32))) sitd_t;
    92 #endif
    93107/**
    94108 * @}

  • uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h

    r4f8772d4 r904b1bc  
    4747
    4848        volatile uint32_t status;
     49
     50        volatile uint32_t buffer_pointer[5];
     51
     52        /* 64 bit struct only */
     53        volatile uint32_t extended_bp[5];
     54
     55} __attribute__((packed, aligned(32))) td_t;
     56
     57/*
     58 * td_t.status
     59 */
    4960#define TD_STATUS_TOGGLE_FLAG   (1 << 31)
    5061#define TD_STATUS_TOTAL_MASK    0x7fff
    … …  
    6980#define TD_STATUS_PING_FLAG     (1 << 0)
    7081
    71         volatile uint32_t buffer_pointer[5];
     82/*
     83 * td_t.buffer_pointer
     84 */
     85
    7286#define TD_BUFFER_POINTER_MASK   0xfffff000
    7387/* Only the first page pointer */
    7488#define TD_BUFFER_POINTER_OFFSET_MASK    0xfff
    75 
    76         /* 64 bit struct only */
    77         volatile uint32_t extended_bp[5];
    78 
    79 } __attribute__((packed, aligned(32))) td_t;
    8089
    8190static_assert(sizeof(td_t) % 32 == 0);

  • uspace/drv/bus/usb/ohci/ohci_regs.h

    r4f8772d4 r904b1bc  
    5050typedef struct ohci_regs {
    5151        const ioport32_t revision;
    52 #define R_REVISION_MASK (0x3f)
    53 #define R_LEGACY_FLAG   (0x80)
    5452
    5553        ioport32_t control;
    56 /* Control-bulk service ratio */
    57 #define C_CBSR_1_1  (0x0)
    58 #define C_CBSR_1_2  (0x1)
    59 #define C_CBSR_1_3  (0x2)
    60 #define C_CBSR_1_4  (0x3)
    61 #define C_CBSR_MASK (0x3)
    62 #define C_CBSR_SHIFT 0
    63 
    64 #define C_PLE (1 << 2)   /* Periodic list enable */
    65 #define C_IE  (1 << 3)   /* Isochronous enable */
    66 #define C_CLE (1 << 4)   /* Control list enable */
    67 #define C_BLE (1 << 5)   /* Bulk list enable */
    68 
    69 /* Host controller functional state */
    70 #define C_HCFS_RESET       (0x0)
    71 #define C_HCFS_RESUME      (0x1)
    72 #define C_HCFS_OPERATIONAL (0x2)
    73 #define C_HCFS_SUSPEND     (0x3)
    74 #define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
    75 #define C_HCFS_SET(reg, value) \
    76 do { \
    77         uint32_t r = OHCI_RD(reg); \
    78         r &= ~(0x3 << 6); \
    79         r |= (value & 0x3) << 6; \
    80         OHCI_WR(reg, r); \
    81 } while (0)
    82 
    83 #define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
    84 #define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
    85 #define C_RWE (1 << 10)  /* Remote wakeup enable */
    8654
    8755        ioport32_t command_status;
    88 #define CS_HCR (1 << 0)   /* Host controller reset */
    89 #define CS_CLF (1 << 1)   /* Control list filled */
    90 #define CS_BLF (1 << 2)   /* Bulk list filled */
    91 #define CS_OCR (1 << 3)   /* Ownership change request */
    92 #if 0
    93 #define CS_SOC_MASK (0x3) /* Scheduling overrun count */
    94 #define CS_SOC_SHIFT (16)
    95 #endif
    9656
    9757        /** Interupt enable/disable/status,
    9858         * reads give the same value,
    9959         * writing causes enable/disable,
    100          * status is write-clean (writing 1 clears the bit*/
     60         * status is write-clean (writing 1 clears the bit
     61         */
    10162        ioport32_t interrupt_status;
    10263        ioport32_t interrupt_enable;
    10364        ioport32_t interrupt_disable;
    104 #define I_SO   (1 << 0)   /* Scheduling overrun */
    105 #define I_WDH  (1 << 1)   /* Done head write-back */
    106 #define I_SF   (1 << 2)   /* Start of frame */
    107 #define I_RD   (1 << 3)   /* Resume detect */
    108 #define I_UE   (1 << 4)   /* Unrecoverable error */
    109 #define I_FNO  (1 << 5)   /* Frame number overflow */
    110 #define I_RHSC (1 << 6)   /* Root hub status change */
    111 #define I_OC   (1 << 30)  /* Ownership change */
    112 #define I_MI   (1 << 31)  /* Master interrupt (any/all) */
    11365
    11466        /** HCCA pointer (see hw_struct hcca.h) */
    11567        ioport32_t hcca;
    116 #define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
    11768
    11869        /** Currently executed periodic endpoint */
    … …  
    13687        /** Frame time and max packet size for all transfers */
    13788        ioport32_t fm_interval;
    138 #define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
    139 #define FMI_FI_SHIFT (0)
    140 #define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
    141 #define FMI_FSMPS_SHIFT (16)
    142 #define FMI_TOGGLE_FLAG (1 << 31)
    14389
    14490        /** Bit times remaining in current frame */
    14591        const ioport32_t fm_remaining;
    146 #define FMR_FR_MASK FMI_FI_MASK
    147 #define FMR_FR_SHIFT FMI_FI_SHIFT
    148 #define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
    14992
    15093        /** Frame number */
    15194        const ioport32_t fm_number;
    152 #define FMN_NUMBER_MASK (0xffff)
    15395
    15496        /** Remaining bit time in frame to start periodic transfers */
    15597        ioport32_t periodic_start;
    156 #define PS_MASK 0x3fff
    157 #define PS_SHIFT 0
    15898
    15999        /** Threshold for starting LS transaction */
    160100        ioport32_t ls_threshold;
    161 #define LST_LST_MASK (0x7fff)
    162101
    163102        /** The first root hub control register */
    164103        ioport32_t rh_desc_a;
    165 /** Number of downstream ports, max 15 */
    166 #define RHDA_NDS_MASK  (0xff)
    167 /** Power switching mode: 0-global, 1-per port*/
    168 #define RHDA_PSM_FLAG  (1 << 8)
    169 /** No power switch: 1-power on, 0-use PSM*/
    170 #define RHDA_NPS_FLAG  (1 << 9)
    171 /** 1-Compound device, must be 0 */
    172 #define RHDA_DT_FLAG   (1 << 10)
    173 /** Over-current mode: 0-global, 1-per port */
    174 #define RHDA_OCPM_FLAG (1 << 11)
    175 /** OC control: 0-use OCPM, 1-OC off */
    176 #define RHDA_NOCP_FLAG (1 << 12)
    177 /** Power on to power good time */
    178 #define RHDA_POTPGT_SHIFT   24
    179104
    180105        /** The other root hub control register */
    181106        ioport32_t rh_desc_b;
    182 /** Device removable mask */
    183 #define RHDB_DR_SHIFT   0
    184 #define RHDB_DR_MASK    0xffffU
    185 /** Power control mask */
    186 #define RHDB_PCC_MASK   0xffffU
    187 #define RHDB_PCC_SHIFT  16
    188107
    189108        /** Root hub status register */
    190109        ioport32_t rh_status;
    191 /* read: 0,
    192  * write: 0-no effect,
    193  *        1-turn off port power for ports
    194  *        specified in PPCM(RHDB), or all ports,
    195  *        if power is set globally */
    196 #define RHS_LPS_FLAG  (1 <<  0)
    197 #define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
    198 /** Over-current indicator, if per-port: 0 */
    199 #define RHS_OCI_FLAG  (1 <<  1)
    200 
    201 /* read: 0-connect status change does not wake HC
    202  *       1-connect status change wakes HC
    203  * write: 1-set DRWE, 0-no effect */
    204 #define RHS_DRWE_FLAG (1 << 15)
    205 #define RHS_SET_DRWE RHS_DRWE_FLAG
    206 /* read: 0,
    207  * write: 0-no effect
    208  *        1-turn on port power for ports
    209  *        specified in PPCM(RHDB), or all ports,
    210  *        if power is set globally */
    211 #define RHS_LPSC_FLAG (1 << 16)
    212 #define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
    213 /** Over-current change indicator*/
    214 #define RHS_OCIC_FLAG (1 << 17)
    215 #define RHS_CLEAR_DRWE (1 << 31)
    216110
    217111        /** Root hub per port status */
    … …  
    249143} ohci_regs_t;
    250144
     145/*
     146 * ohci_regs_t.revision
     147 */
     148
     149#define R_REVISION_MASK (0x3f)
     150#define R_LEGACY_FLAG   (0x80)
     151
     152/*
     153 * ohci_regs_t.control
     154 */
     155 
     156/* Control-bulk service ratio */
     157#define C_CBSR_1_1  (0x0)
     158#define C_CBSR_1_2  (0x1)
     159#define C_CBSR_1_3  (0x2)
     160#define C_CBSR_1_4  (0x3)
     161#define C_CBSR_MASK (0x3)
     162#define C_CBSR_SHIFT 0
     163
     164#define C_PLE (1 << 2)   /* Periodic list enable */
     165#define C_IE  (1 << 3)   /* Isochronous enable */
     166#define C_CLE (1 << 4)   /* Control list enable */
     167#define C_BLE (1 << 5)   /* Bulk list enable */
     168
     169/* Host controller functional state */
     170#define C_HCFS_RESET       (0x0)
     171#define C_HCFS_RESUME      (0x1)
     172#define C_HCFS_OPERATIONAL (0x2)
     173#define C_HCFS_SUSPEND     (0x3)
     174#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
     175#define C_HCFS_SET(reg, value) \
     176do { \
     177        uint32_t r = OHCI_RD(reg); \
     178        r &= ~(0x3 << 6); \
     179        r |= (value & 0x3) << 6; \
     180        OHCI_WR(reg, r); \
     181} while (0)
     182
     183#define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
     184#define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
     185#define C_RWE (1 << 10)  /* Remote wakeup enable */
     186
     187/*
     188 * ohci_regs_t.command_status
     189 */
     190
     191#define CS_HCR (1 << 0)   /* Host controller reset */
     192#define CS_CLF (1 << 1)   /* Control list filled */
     193#define CS_BLF (1 << 2)   /* Bulk list filled */
     194#define CS_OCR (1 << 3)   /* Ownership change request */
     195#if 0
     196#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
     197#define CS_SOC_SHIFT (16)
    251198#endif
     199
     200/*
     201 * ohci_regs_t.interrupt_xxx
     202 */
     203
     204#define I_SO   (1 << 0)   /* Scheduling overrun */
     205#define I_WDH  (1 << 1)   /* Done head write-back */
     206#define I_SF   (1 << 2)   /* Start of frame */
     207#define I_RD   (1 << 3)   /* Resume detect */
     208#define I_UE   (1 << 4)   /* Unrecoverable error */
     209#define I_FNO  (1 << 5)   /* Frame number overflow */
     210#define I_RHSC (1 << 6)   /* Root hub status change */
     211#define I_OC   (1 << 30)  /* Ownership change */
     212#define I_MI   (1 << 31)  /* Master interrupt (any/all) */
     213
     214
     215/*
     216 * ohci_regs_t.hcca
     217 */
     218
     219#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
     220
     221/*
     222 * ohci_regs_t.fm_interval
     223 */
     224
     225#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
     226#define FMI_FI_SHIFT (0)
     227#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
     228#define FMI_FSMPS_SHIFT (16)
     229#define FMI_TOGGLE_FLAG (1 << 31)
     230
     231/*
     232 * ohci_regs_t.fm_remaining
     233 */
     234
     235#define FMR_FR_MASK FMI_FI_MASK
     236#define FMR_FR_SHIFT FMI_FI_SHIFT
     237#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
     238
     239/*
     240 * ohci_regs_t.fm_number
     241 */
     242
     243#define FMN_NUMBER_MASK (0xffff)
     244
     245/*
     246 * ohci_regs_t.periodic_start
     247 */
     248
     249#define PS_MASK 0x3fff
     250#define PS_SHIFT 0
     251
     252/*
     253 * ohci_regs_t.ls_threshold
     254 */
     255
     256#define LST_LST_MASK (0x7fff)
     257
     258/*
     259 * ohci_regs_t.rh_desc_a
     260 */
     261
     262/** Number of downstream ports, max 15 */
     263#define RHDA_NDS_MASK  (0xff)
     264/** Power switching mode: 0-global, 1-per port*/
     265#define RHDA_PSM_FLAG  (1 << 8)
     266/** No power switch: 1-power on, 0-use PSM*/
     267#define RHDA_NPS_FLAG  (1 << 9)
     268/** 1-Compound device, must be 0 */
     269#define RHDA_DT_FLAG   (1 << 10)
     270/** Over-current mode: 0-global, 1-per port */
     271#define RHDA_OCPM_FLAG (1 << 11)
     272/** OC control: 0-use OCPM, 1-OC off */
     273#define RHDA_NOCP_FLAG (1 << 12)
     274/** Power on to power good time */
     275#define RHDA_POTPGT_SHIFT   24
     276
     277/*
     278 * ohci_regs_t.rh_desc_b
     279 */
     280
     281/** Device removable mask */
     282#define RHDB_DR_SHIFT   0
     283#define RHDB_DR_MASK    0xffffU
     284
     285/** Power control mask */
     286#define RHDB_PCC_MASK   0xffffU
     287#define RHDB_PCC_SHIFT  16
     288
     289/*
     290 * ohci_regs_t.rh_status
     291 */
     292
     293/*
     294 * read: 0,
     295 * write: 0-no effect,
     296 *        1-turn off port power for ports
     297 *        specified in PPCM(RHDB), or all ports,
     298 *        if power is set globally
     299 */
     300#define RHS_LPS_FLAG  (1 <<  0)
     301#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
     302/** Over-current indicator, if per-port: 0 */
     303#define RHS_OCI_FLAG  (1 <<  1)
     304/*
     305 * read: 0-connect status change does not wake HC
     306 *       1-connect status change wakes HC
     307 * write: 1-set DRWE, 0-no effect
     308 */
     309#define RHS_DRWE_FLAG (1 << 15)
     310#define RHS_SET_DRWE RHS_DRWE_FLAG
     311/*
     312 * read: 0,
     313 * write: 0-no effect
     314 *        1-turn on port power for ports
     315 *        specified in PPCM(RHDB), or all ports,
     316 *        if power is set globally
     317 */
     318#define RHS_LPSC_FLAG (1 << 16)
     319#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
     320/** Over-current change indicator*/
     321#define RHS_OCIC_FLAG (1 << 17)
     322#define RHS_CLEAR_DRWE (1 << 31)
     323
     324#endif
     325
     326/*
     327 * ohci_regs_t.rh_port_status[x]
     328 */
     329
     330/** r: current connect status, w: 1-clear port enable, 0-N/S*/
     331#define RHPS_CCS_FLAG (1 << 0)
     332#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
     333/** r: port enable status, w: 1-set port enable, 0-N/S */
     334#define RHPS_PES_FLAG (1 << 1)
     335#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
     336/** r: port suspend status, w: 1-set port suspend, 0-N/S */
     337#define RHPS_PSS_FLAG (1 << 2)
     338#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
     339/** r: port over-current (if reports are per-port
     340 * w: 1-clear port suspend (start resume if suspened), 0-nothing
     341 */
     342#define RHPS_POCI_FLAG (1 << 3)
     343#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
     344/** r: port reset status, w: 1-set port reset, 0-N/S */
     345#define RHPS_PRS_FLAG (1 << 4)
     346#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
     347/** r: port power status, w: 1-set port power, 0-N/S */
     348#define RHPS_PPS_FLAG (1 << 8)
     349#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
     350/** r: low speed device attached, w: 1-clear port power, 0-N/S */
     351#define RHPS_LSDA_FLAG (1 << 9)
     352#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
     353/** connect status change WC */
     354#define RHPS_CSC_FLAG  (1 << 16)
     355/** port enable status change WC */
     356#define RHPS_PESC_FLAG (1 << 17)
     357/** port suspend status change WC */
     358#define RHPS_PSSC_FLAG (1 << 18)
     359/** port over-current change WC */
     360#define RHPS_OCIC_FLAG (1 << 19)
     361/** port reset status change WC */
     362#define RHPS_PRSC_FLAG (1 << 20)
     363#define RHPS_CHANGE_WC_MASK (0x1f0000)
    252364
    253365/**

  • uspace/drv/bus/usb/uhci/hc.c

    r4f8772d4 r904b1bc  
    531531            &instance->transfers_control_slow);
    532532
    533         /*FSBR, This feature is not needed (adds no benefit) and is supposedly
    534          * buggy on certain hw, enable at your own risk. */
     533        /*
     534         * FSBR, This feature is not needed (adds no benefit) and is supposedly
     535         * buggy on certain hw, enable at your own risk.
     536         */
    535537#ifdef FSBR
    536538        transfer_list_set_next(&instance->transfers_bulk_full,

  • uspace/drv/bus/usb/xhci/commands.h

    r4f8772d4 r904b1bc  
    7979        xhci_trb_ring_t trb_ring;
    8080
    81         fibril_mutex_t guard;           /**< Guard access to this structure. */
     81        /** Guard access to this structure. */
     82        fibril_mutex_t guard;
    8283        list_t cmd_list;
    8384
    84         xhci_cr_state_t state;          /**< Whether commands are allowed to be
    85                                              added. */
    86         fibril_condvar_t state_cv;      /**< For waiting on CR state change. */
     85        /** Whether commands are allowed to be added. */
     86        xhci_cr_state_t state;
     87        /** For waiting on CR state change. */
     88        fibril_condvar_t state_cv;
    8789
    88         fibril_condvar_t stopped_cv;    /**< For waiting on CR stopped event. */
     90        /** For waiting on CR stopped event. */
     91        fibril_condvar_t stopped_cv;
    8992} xhci_cmd_ring_t;
    9093
    … …  
    108111
    109112        /** Below are arguments of all commands mixed together.
    110          *  Be sure to know which command accepts what arguments. */
     113         *  Be sure to know which command accepts what arguments.
     114         */
    111115
    112116        uint32_t slot_id;
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