Changeset 904b1bc in mainline for uspace/drv


Ignore:
Timestamp:
2018-05-22T10:36:58Z (8 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a4eb3ba2
Parents:
4f8772d4
git-author:
Jiri Svoboda <jiri@…> (2018-05-21 17:36:30)
git-committer:
Jiri Svoboda <jiri@…> (2018-05-22 10:36:58)
Message:

Fix remaining ccheck issues.

Location:
uspace/drv
Files:
10 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/audio/sb16/dsp_commands.h

    r4f8772d4 r904b1bc  
    3838/** See Sound Blaster Series HW programming Guide Chapter 6. */
    3939typedef enum dsp_command {
    40         DIRECT_8B_OUTPUT = 0x10, /* Followed by unsigned byte of digital data,
    41                                   * software controls sampling rate */
    42         DIRECT_8B_INPUT = 0x20,  /* Same as DIRECT_8B_OUTPUT but for input */
    43 
    44         TRANSFER_TIME_CONSTANT = 0x40, /* Followed by time constant.
    45                                         * TC = 65536 - (256 000 000 /
    46                                         *   (channels * sampling rate))
    47                                         * Send only high byte */
    48 
    49         SINGLE_DMA_8B_OUTPUT = 0x14, /* Followed by length.high and length.low
    50                                       * starts single-cycle DMA, length is -1 */
    51         SINGLE_DMA_8B_INPUT = 0x24,  /* Same as SINGLE_DMA_8B_OUTPUT, but for
    52                                       * input */
    53         SINGLE_DMA_8B_ADPCM_2B_OUT = 0x16, /* Starts single-cycle DMA using
    54                                             * Creative ADPSM 8->2 bit compressed
    55                                             * data, Followed by length.low
    56                                             * and length.high. Length is -1 */
    57         SINGLE_DMA_8B_ADPCM_2B_OUT_REF = 0x17, /* Starts single-cycle DMA using
    58                                                 * DPSM 8->2 bit compressed data
    59                                                 * with reference byte.
    60                                                 * Followed by length.low and
    61                                                 * length.high. Length is -1 */
    62         SINGLE_DMA_8B_ADPCM_4B_OUT = 0x74, /* Same as
    63                                             * SINGLE_DMA_8B_ADPCM_2B_OUT */
    64         SINGLE_DMA_8B_ADPCM_4B_OUT_REF = 0x75, /* Same as
    65                                                 * SINGLE_DMA_8B_ADPCM_2B_OUT_REF
    66                                                 */
    67         SINGLE_DMA_8B_ADPCM_3B_OUT = 0x76, /* Same as
    68                                             * SINGLE_DMA_8B_ADPCM_2B_OUT */
    69         SINGLE_DMA_8B_ADPCM_3B_OUT_REF = 0x77, /* Same as
    70                                                 * SINGLE_DMA_8B_ADPCM_2B_OUT_REF
    71                                                 */
    72 
    73         DMA_8B_PAUSE = 0xd0, /* Stop sending DMA request,
    74                               * works for SINGLE and AUTO */
    75         DMA_8B_CONTINUE = 0xd4, /* Resume transfers paused by DMA_8B_PAUSE */
    76 
    77         SPEAKER_ON = 0xd1,  /* Connect speaker via internal amplifier,
    78                              * has no effect on 4.xx */
    79         SPEAKER_OFF = 0xd3, /* Disconnect output from the amplifier,
    80                              * has no effect on 4.xx */
    81 
    82         MIDI_POLLING = 0x30, /* Read DSP for MIDI data */
    83         MIDI_INTERRUPT = 0x31, /* Start interrupt mode, interrupt will be
    84                                 * generated when there is in-bound data.
    85                                 * To exit send again */
    86         MIDI_OUTPUT = 0x38, /* Followed by midi_data */
    87 
    88         PAUSE = 0x80, /* Followed by duration.low, duration.high. Duration is -1
    89                        * In the units of sampling period. Generates interrupt
    90                        * at the end of period */
    91         DSP_VERSION = 0xe1, /* Read 2 bytes, major and minor number */
    92 
    93         AUTO_DMA_8B_OUTPUT = 0x1c, /* Starts auto-init DMA mode using 8-bit
    94                                     * Interrupt after every block.
    95                                     * To terminate, switch to single or use
    96                                     * EXIT command*/
    97         AUTO_DMA_8B_INPUT = 0x2c, /* Same as AUTO_DMA_8B_OUTPUT, but for input*/
    98         AUTO_DMA_8B_ADPCM_2B_REF = 0x1f, /* Same as AUTO_DMA_8B_OUTPUT, but use
    99                                           * 8->2bit ADPCM audio format */
    100         AUTO_DMA_8B_ADPCM_4B_REF = 0x7d, /* Same as AUTO_DMA_8B_ADPCM_2B_REF */
    101         AUTO_DMA_8B_ADPCM_3B_REF = 0x7f, /* Same as AUTO_DMA_8B_ADPCM_2B_REF */
    102 
    103         DMA_8B_EXIT = 0xda, /* Ends DMA transfer and terminates I/O process */
    104 
    105         BLOCK_TRANSFER_SIZE = 0x48, /* Followed by size.low, size.high
    106                                      * Used with HIGH_SPEED AUTO_DMA */
    107 
    108         UART_MIDI_POLLING = 0x34, /* Start UART MIDI polling mode, read and
    109                                    * write from/to DSP is interpreted as
    110                                    * read/write from/to MIDI.
    111                                    * To exit use reset signal. Note that reset
    112                                    * will restore previous state and won't do
    113                                    * complete reset */
    114         UART_MIDI_INTERRUPT = 0x35, /* Same as UART_MIDI_POLLING, but use
    115                                      * interrupts instead of polling. */
    116         UART_MIDI_POLLING_TS = 0x36, /* Add time stamp to inbound data, the
    117                                       * order is time.low time.mid time.high
    118                                       * data */
    119         UART_MIDI_INTERRUPT_TS = 0x37, /* Same as UART_MIDI_POLLING_TS, but use
    120                                         * interrupts instead of polling */
    121 
    122         SPEAKER_STATUS = 0xd8, /* 0xff means amp is on, 0x00 means it's off */
    123 
    124         AUTO_DMA_8B_HIGH_OUTPUT = 0x90, /* DSP will generate interrupt after
    125                                          * every block. No other commands are
    126                                          * accepted in this mode. To exit
    127                                          * the mode send RESET command.
    128                                          * Note that reset will restore
    129                                          * previous state. */
    130         AUTO_DMA_8B_HIGH_INPUT = 0x98, /* Same as AUTO_DMA_8B_HIGH_OUTPUT */
    131         SINGLE_DMA_8B_HIGH_OUTPUT = 0x91, /* Transfer one block and exit,
    132                                            * generates interrupt */
    133         SINGLE_DMA_8B_HIGH_INPUT = 0x99, /* Same as SINGLE_DMA_8B_HIGH_OUTPUT */
    134 
    135         SET_MONO_INPUT = 0xa0, /* Mono mode is the default, only on 3.xx */
    136         SET_STEREO_INPUT = 0xa8, /* Switch to stereo recording, only on 3.xx */
    137 
    138         SET_SAMPLING_RATE_OUTPUT = 0x41, /* Followed by sapling rate
    139                                           * 5000 to 45000 Hz, inclusive */
    140         SET_SAMPLING_RATE_INPUT = 0x42, /* Same as SET_SAMPLING_RATE_OUTPUT */
    141 
    142         SINGLE_DMA_16B_DA = 0xb0,     /* Followed by mode, size.low, size.high*/
    143         SINGLE_DMA_16B_DA_FIFO = 0xb2,/* mode format is:                      */
    144         AUTO_DMA_16B_DA = 0xb4,       /*    0x00 - unsigned mono              */
    145         AUTO_DMA_16B_DA_FIFO = 0xb6,  /*    0x10 - signed mono                */
    146         SINGLE_DMA_16B_AD = 0xb8,     /*    0x20 - unsigned stereo            */
    147         SINGLE_DMA_16B_AD_FIFO = 0xba,/*    0x30 - signed stereo              */
    148         AUTO_DMA_16B_AD = 0xbc,       /* Size is -1. Terminate by EXIT        */
    149         AUTO_DMA_16B_AD_FIFO = 0xbe,  /* or switch to SINGLE_DMA              */
    150 
    151         SINGLE_DMA_8B_DA = 0xc0,     /* Followed by mode, size.low, size.high */
    152         SINGLE_DMA_8B_DA_FIFO = 0xc2,/* mode format is:                       */
    153         AUTO_DMA_8B_DA = 0xc4,       /*    0x00 - unsigned mono               */
    154         AUTO_DMA_8B_DA_FIFO = 0xc6,  /*    0x10 - signed mono                 */
    155         SINGLE_DMA_8B_AD = 0xc8,     /*    0x20 - unsigned stereo             */
    156         SINGLE_DMA_8B_AD_FIFO = 0xca,/*    0x30 - signed stereo               */
    157         AUTO_DMA_8B_AD = 0xcc,       /* Size is -1. Terminate by EXIT         */
    158         AUTO_DMA_8B_AD_FIFO = 0xce,  /* or switch to SINGLE_DMA               */
    159 
    160         DMA_16B_PAUSE = 0xd5,/* Stop sending DMA request, both SINGLE and AUTO*/
    161         DMA_16B_CONTINUE = 0xd6, /* Resume requests paused by DMA_16B_PAUSE */
    162         DMA_16B_EXIT = 0xd9, /* Ends DMA transfer and terminates I/O process */
     40        /*
     41         * Followed by unsigned byte of digital data,
     42         * software controls sampling rate
     43         */
     44        DIRECT_8B_OUTPUT = 0x10,
     45        /* Same as DIRECT_8B_OUTPUT but for input */
     46        DIRECT_8B_INPUT = 0x20,
     47
     48        /*
     49         * Followed by time constant.
     50         * TC = 65536 - (256 000 000 /
     51         *   (channels * sampling rate))
     52         * Send only high byte
     53         */
     54        TRANSFER_TIME_CONSTANT = 0x40,
     55
     56        /*
     57         * Followed by length.high and length.low
     58         * starts single-cycle DMA, length is -1
     59         */
     60        SINGLE_DMA_8B_OUTPUT = 0x14,
     61        /*
     62         * Same as SINGLE_DMA_8B_OUTPUT, but for
     63         * input
     64         */
     65        SINGLE_DMA_8B_INPUT = 0x24,
     66        /*
     67         * Starts single-cycle DMA using
     68         * Creative ADPSM 8->2 bit compressed
     69         * data, Followed by length.low
     70         * and length.high. Length is -1
     71         */
     72        SINGLE_DMA_8B_ADPCM_2B_OUT = 0x16,
     73        /*
     74         * Starts single-cycle DMA using
     75         * DPSM 8->2 bit compressed data
     76         * with reference byte.
     77         * Followed by length.low and
     78         * length.high. Length is -1
     79         */
     80        SINGLE_DMA_8B_ADPCM_2B_OUT_REF = 0x17,
     81        /*
     82         * Same as
     83         * SINGLE_DMA_8B_ADPCM_2B_OUT
     84         */
     85        SINGLE_DMA_8B_ADPCM_4B_OUT = 0x74,
     86        /*
     87         * Same as
     88         * SINGLE_DMA_8B_ADPCM_2B_OUT_REF
     89         */
     90        SINGLE_DMA_8B_ADPCM_4B_OUT_REF = 0x75,
     91        /*
     92         * Same as
     93         * SINGLE_DMA_8B_ADPCM_2B_OUT
     94         */
     95        SINGLE_DMA_8B_ADPCM_3B_OUT = 0x76,
     96        /*
     97         * Same as
     98         * SINGLE_DMA_8B_ADPCM_2B_OUT_REF
     99         */
     100        SINGLE_DMA_8B_ADPCM_3B_OUT_REF = 0x77,
     101        /*
     102         * Stop sending DMA request,
     103         * works for SINGLE and AUTO
     104         */
     105        DMA_8B_PAUSE = 0xd0,
     106        /* Resume transfers paused by DMA_8B_PAUSE */
     107        DMA_8B_CONTINUE = 0xd4,
     108
     109        /*
     110         * Connect speaker via internal amplifier,
     111         * has no effect on 4.xx
     112         */
     113        SPEAKER_ON = 0xd1,
     114        /*
     115         * Disconnect output from the amplifier,
     116         * has no effect on 4.xx
     117         */
     118        SPEAKER_OFF = 0xd3,
     119
     120        /* Read DSP for MIDI data */
     121        MIDI_POLLING = 0x30,
     122        /*
     123         * Start interrupt mode, interrupt will be
     124         * generated when there is in-bound data.
     125         * To exit send again
     126         */
     127        MIDI_INTERRUPT = 0x31,
     128        /* Followed by midi_data */
     129        MIDI_OUTPUT = 0x38,
     130
     131        /*
     132         * Followed by duration.low, duration.high. Duration is -1
     133         * In the units of sampling period. Generates interrupt
     134         * at the end of period
     135         */
     136        PAUSE = 0x80,
     137        /* Read 2 bytes, major and minor number */
     138        DSP_VERSION = 0xe1,
     139
     140        /*
     141         * Starts auto-init DMA mode using 8-bit
     142         * Interrupt after every block.
     143         * To terminate, switch to single or use
     144         * EXIT command
     145         */
     146        AUTO_DMA_8B_OUTPUT = 0x1c,
     147        /* Same as AUTO_DMA_8B_OUTPUT, but for input */
     148        AUTO_DMA_8B_INPUT = 0x2c,
     149        /*
     150         * Same as AUTO_DMA_8B_OUTPUT, but use
     151         * 8->2bit ADPCM audio format
     152         */
     153        AUTO_DMA_8B_ADPCM_2B_REF = 0x1f,
     154        /* Same as AUTO_DMA_8B_ADPCM_2B_REF */
     155        AUTO_DMA_8B_ADPCM_4B_REF = 0x7d,
     156        /* Same as AUTO_DMA_8B_ADPCM_2B_REF */
     157        AUTO_DMA_8B_ADPCM_3B_REF = 0x7f,
     158
     159        /* Ends DMA transfer and terminates I/O process */
     160        DMA_8B_EXIT = 0xda,
     161
     162        /*
     163         * Followed by size.low, size.high
     164         * Used with HIGH_SPEED AUTO_DMA
     165         */
     166        BLOCK_TRANSFER_SIZE = 0x48,
     167        /*
     168         * Start UART MIDI polling mode, read and
     169         * write from/to DSP is interpreted as
     170         * read/write from/to MIDI.
     171         * To exit use reset signal. Note that reset
     172         * will restore previous state and won't do
     173         * complete reset
     174         */
     175        UART_MIDI_POLLING = 0x34,
     176        /*
     177         * Same as UART_MIDI_POLLING, but use
     178         * interrupts instead of polling.
     179         */
     180        UART_MIDI_INTERRUPT = 0x35,
     181        /*
     182         * Add time stamp to inbound data, the
     183         * order is time.low time.mid time.high
     184         * data
     185         */
     186        UART_MIDI_POLLING_TS = 0x36,
     187        /*
     188         * Same as UART_MIDI_POLLING_TS, but use
     189         * interrupts instead of polling
     190         */
     191        UART_MIDI_INTERRUPT_TS = 0x37,
     192
     193        /* 0xff means amp is on, 0x00 means it's off */
     194        SPEAKER_STATUS = 0xd8,
     195
     196        /*
     197         * DSP will generate interrupt after
     198         * every block. No other commands are
     199         * accepted in this mode. To exit
     200         * the mode send RESET command.
     201         * Note that reset will restore
     202         * previous state.
     203         */
     204        AUTO_DMA_8B_HIGH_OUTPUT = 0x90,
     205        /* Same as AUTO_DMA_8B_HIGH_OUTPUT */
     206        AUTO_DMA_8B_HIGH_INPUT = 0x98,
     207        /*
     208         * Transfer one block and exit,
     209         * generates interrupt
     210         */
     211        SINGLE_DMA_8B_HIGH_OUTPUT = 0x91,
     212        /* Same as SINGLE_DMA_8B_HIGH_OUTPUT */
     213        SINGLE_DMA_8B_HIGH_INPUT = 0x99,
     214
     215        /* Mono mode is the default, only on 3.xx */
     216        SET_MONO_INPUT = 0xa0,
     217        /* Switch to stereo recording, only on 3.xx */
     218        SET_STEREO_INPUT = 0xa8,
     219
     220        /*
     221         * Followed by sapling rate
     222         * 5000 to 45000 Hz, inclusive
     223         */
     224        SET_SAMPLING_RATE_OUTPUT = 0x41,
     225        /* Same as SET_SAMPLING_RATE_OUTPUT */
     226        SET_SAMPLING_RATE_INPUT = 0x42,
     227
     228        /*
     229         * Followed by mode, size.low, size.high
     230         * mode format is:
     231         *    0x00 - unsigned mono
     232         *    0x10 - signed mono
     233         *    0x20 - unsigned stereo
     234         *    0x30 - signed stereo
     235         * Size is -1. Terminate AUTO_DMA by EXIT
     236         * or switch to SINGLE_DMA
     237         */
     238        SINGLE_DMA_16B_DA = 0xb0,
     239        SINGLE_DMA_16B_DA_FIFO = 0xb2,
     240        AUTO_DMA_16B_DA = 0xb4,
     241        AUTO_DMA_16B_DA_FIFO = 0xb6,
     242        SINGLE_DMA_16B_AD = 0xb8,
     243        SINGLE_DMA_16B_AD_FIFO = 0xba,
     244        AUTO_DMA_16B_AD = 0xbc,
     245        AUTO_DMA_16B_AD_FIFO = 0xbe,
     246
     247        /*
     248         * Followed by mode, size.low, size.high
     249         * mode format is:
     250         *    0x00 - unsigned mono
     251         *    0x10 - signed mono
     252         *    0x20 - unsigned stereo
     253         *    0x30 - signed stereo
     254         * Size is -1. Terminate AUTO_DMA by EXIT
     255         * or switch to SINGLE_DMA
     256         */
     257        SINGLE_DMA_8B_DA = 0xc0,
     258        SINGLE_DMA_8B_DA_FIFO = 0xc2,
     259        AUTO_DMA_8B_DA = 0xc4,
     260        AUTO_DMA_8B_DA_FIFO = 0xc6,
     261        SINGLE_DMA_8B_AD = 0xc8,
     262        SINGLE_DMA_8B_AD_FIFO = 0xca,
     263        AUTO_DMA_8B_AD = 0xcc,
     264        AUTO_DMA_8B_AD_FIFO = 0xce,
     265
     266        /* Stop sending DMA request, both SINGLE and AUTO */
     267        DMA_16B_PAUSE = 0xd5,
     268        /* Resume requests paused by DMA_16B_PAUSE */
     269        DMA_16B_CONTINUE = 0xd6,
     270        /* Ends DMA transfer and terminates I/O process */
     271        DMA_16B_EXIT = 0xd9,
    163272} dsp_command_t;
    164273

  • uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h

    r4f8772d4 r904b1bc  
    4343
    4444        volatile uint32_t transaction[8];
     45        volatile uint32_t buffer_pointer[7];
     46
     47        /* 64 bit struct only */
     48        volatile uint32_t extended_bp[7];
     49} __attribute__((packed, aligned(32))) itd_t;
     50
     51/*
     52 * itd_t.transaction
     53 */
    4554#define ITD_TRANSACTION_STATUS_ACTIVE_FLAG  (1 << 31)
    4655#define ITD_TRANSACTION_STATUS_BUFFER_ERROR_FLAG  (1 << 30)
    … …  
    5564#define ITD_TRANSACTION_OFFSET_SHIFT   0
    5665
    57         volatile uint32_t buffer_pointer[7];
     66/*
     67 * itd_t.buffer_pointer
     68 */
    5869#define ITD_BUFFER_POINTER_MASK      0xfffff000
    5970/* First buffer pointer */
    … …  
    7081#define ITD_BUFFER_POINTER_MULTI_SHIFT   0
    7182
    72         /* 64 bit struct only */
    73         volatile uint32_t extended_bp[7];
    74 } __attribute__((packed, aligned(32))) itd_t;
    7583#endif
     84
    7685/**
    7786 * @}

  • uspace/drv/bus/usb/ehci/hw_struct/queue_head.h

    r4f8772d4 r904b1bc  
    4949
    5050        volatile uint32_t ep_char;
     51        volatile uint32_t ep_cap;
     52
     53        link_pointer_t current;
     54        /* Transfer overlay starts here */
     55        link_pointer_t next;
     56        link_pointer_t alternate;
     57        volatile uint32_t status;
     58        volatile uint32_t buffer_pointer[5];
     59
     60        /* 64 bit struct only */
     61        volatile uint32_t extended_bp[5];
     62} __attribute__((packed, aligned(32))) qh_t;
     63
     64/*
     65 * qh_t.ep_char
     66 */
    5167#define QH_EP_CHAR_RL_MASK    0xf
    5268#define QH_EP_CHAR_RL_SHIFT   28
    … …  
    7894    (((val) >> QH_EP_CHAR_ADDR_SHIFT) & QH_EP_CHAR_ADDR_MASK)
    7995
    80         volatile uint32_t ep_cap;
     96/*
     97 * qh_t.ep_cap
     98 */
    8199#define QH_EP_CAP_MULTI_MASK   0x3
    82100#define QH_EP_CAP_MULTI_SHIFT  30
    … …  
    100118        (((val) & QH_EP_CAP_S_MASK_MASK) << QH_EP_CAP_S_MASK_SHIFT)
    101119
    102         link_pointer_t current;
    103 /* Transfer overlay starts here */
    104         link_pointer_t next;
    105         link_pointer_t alternate;
     120/*
     121 * qh_t.alternate
     122 */
    106123#define QH_ALTERNATE_NACK_CNT_MASK   0x7
    107124#define QH_ALTERNATE_NACK_CNT_SHIFT  1
    108125
    109         volatile uint32_t status;
     126/*
     127 * qh_t.status
     128 */
    110129#define QH_STATUS_TOGGLE_FLAG   (1 << 31)
    111130#define QH_STATUS_TOTAL_MASK    0x7fff
    … …  
    127146#define QH_STATUS_PING_FLAG     (1 << 0)
    128147
    129         volatile uint32_t buffer_pointer[5];
     148/*
     149 * qh_t.buffer_pointer
     150 */
    130151#define QH_BUFFER_POINTER_MASK   0xfffff000
    131152/* Only the first buffer pointer */
    … …  
    141162#define QH_BUFFER_POINTER_FTAG_SHIFT  0
    142163
    143         /* 64 bit struct only */
    144         volatile uint32_t extended_bp[5];
    145 } __attribute__((packed, aligned(32))) qh_t;
    146164
    147165static inline void qh_append_qh(qh_t *qh, const qh_t *next)
    … …  
    212230}
    213231
    214 
    215 void qh_init(qh_t *instance, const endpoint_t *ep);
     232extern void qh_init(qh_t *instance, const endpoint_t *ep);
     233
    216234#endif
    217235/**

  • uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h

    r4f8772d4 r904b1bc  
    4343
    4444        volatile uint32_t ep;
     45        volatile uint32_t uframe;
     46        volatile uint32_t status;
     47        volatile uint32_t buffer_pointer[2];
     48        link_pointer_t back;
     49
     50        /* 64 bit struct only */
     51        volatile uint32_t extended_bp[2];
     52} __attribute__((packed, aligned(32))) sitd_t;
     53
     54/*
     55 * sitd_t.ep
     56 */
    4557#define SITD_EP_IN_FLAG         (1 << 31)
    4658#define SITD_EP_PORT_MASK       0x3f
    … …  
    5365#define SITD_EP_ADDR_SHIFT      0
    5466
    55         volatile uint32_t uframe;
     67/*
     68 * sitd_t.uframe
     69 */
    5670#define SITD_uFRAME_CMASK_MASK    0xff
    5771#define SITD_uFRAME_CMASK_SHIFT   8
    … …  
    5973#define SITD_uFRAME_SMASK_SHIFT   0
    6074
    61         volatile uint32_t status;
     75/*
     76 * sitd_t.status
     77 */
    6278#define SITD_STATUS_IOC_FLAG            (1 << 31)
    6379#define SITD_STATUS_PAGE_FLAG           (1 << 30)
    … …  
    7490#define SITD_STATUS_SPLIT_COMPLETE_FLAG (1 << 1)
    7591
    76         volatile uint32_t buffer_pointer[2];
     92/*
     93 * sitd_t.buffer_pointer
     94 */
    7795#define SITD_BUFFER_POINTER_MASK   0xfffff000
    7896/* Only the first page pointer */
    … …  
    85103#define SITD_BUFFER_POINTER_COUNT_SHIFT   0
    86104
    87         link_pointer_t back;
     105#endif
    88106
    89         /* 64 bit struct only */
    90         volatile uint32_t extended_bp[2];
    91 } __attribute__((packed, aligned(32))) sitd_t;
    92 #endif
    93107/**
    94108 * @}

  • uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h

    r4f8772d4 r904b1bc  
    4747
    4848        volatile uint32_t status;
     49
     50        volatile uint32_t buffer_pointer[5];
     51
     52        /* 64 bit struct only */
     53        volatile uint32_t extended_bp[5];
     54
     55} __attribute__((packed, aligned(32))) td_t;
     56
     57/*
     58 * td_t.status
     59 */
    4960#define TD_STATUS_TOGGLE_FLAG   (1 << 31)
    5061#define TD_STATUS_TOTAL_MASK    0x7fff
    … …  
    6980#define TD_STATUS_PING_FLAG     (1 << 0)
    7081
    71         volatile uint32_t buffer_pointer[5];
     82/*
     83 * td_t.buffer_pointer
     84 */
     85
    7286#define TD_BUFFER_POINTER_MASK   0xfffff000
    7387/* Only the first page pointer */
    7488#define TD_BUFFER_POINTER_OFFSET_MASK    0xfff
    75 
    76         /* 64 bit struct only */
    77         volatile uint32_t extended_bp[5];
    78 
    79 } __attribute__((packed, aligned(32))) td_t;
    8089
    8190static_assert(sizeof(td_t) % 32 == 0);

  • uspace/drv/bus/usb/ohci/ohci_regs.h

    r4f8772d4 r904b1bc  
    5050typedef struct ohci_regs {
    5151        const ioport32_t revision;
    52 #define R_REVISION_MASK (0x3f)
    53 #define R_LEGACY_FLAG   (0x80)
    5452
    5553        ioport32_t control;
    56 /* Control-bulk service ratio */
    57 #define C_CBSR_1_1  (0x0)
    58 #define C_CBSR_1_2  (0x1)
    59 #define C_CBSR_1_3  (0x2)
    60 #define C_CBSR_1_4  (0x3)
    61 #define C_CBSR_MASK (0x3)
    62 #define C_CBSR_SHIFT 0
    63 
    64 #define C_PLE (1 << 2)   /* Periodic list enable */
    65 #define C_IE  (1 << 3)   /* Isochronous enable */
    66 #define C_CLE (1 << 4)   /* Control list enable */
    67 #define C_BLE (1 << 5)   /* Bulk list enable */
    68 
    69 /* Host controller functional state */
    70 #define C_HCFS_RESET       (0x0)
    71 #define C_HCFS_RESUME      (0x1)
    72 #define C_HCFS_OPERATIONAL (0x2)
    73 #define C_HCFS_SUSPEND     (0x3)
    74 #define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
    75 #define C_HCFS_SET(reg, value) \
    76 do { \
    77         uint32_t r = OHCI_RD(reg); \
    78         r &= ~(0x3 << 6); \
    79         r |= (value & 0x3) << 6; \
    80         OHCI_WR(reg, r); \
    81 } while (0)
    82 
    83 #define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
    84 #define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
    85 #define C_RWE (1 << 10)  /* Remote wakeup enable */
    8654
    8755        ioport32_t command_status;
    88 #define CS_HCR (1 << 0)   /* Host controller reset */
    89 #define CS_CLF (1 << 1)   /* Control list filled */
    90 #define CS_BLF (1 << 2)   /* Bulk list filled */
    91 #define CS_OCR (1 << 3)   /* Ownership change request */
    92 #if 0
    93 #define CS_SOC_MASK (0x3) /* Scheduling overrun count */
    94 #define CS_SOC_SHIFT (16)
    95 #endif
    9656
    9757        /** Interupt enable/disable/status,
    9858         * reads give the same value,
    9959         * writing causes enable/disable,
    100          * status is write-clean (writing 1 clears the bit*/
     60         * status is write-clean (writing 1 clears the bit
     61         */
    10162        ioport32_t interrupt_status;
    10263        ioport32_t interrupt_enable;
    10364        ioport32_t interrupt_disable;
    104 #define I_SO   (1 << 0)   /* Scheduling overrun */
    105 #define I_WDH  (1 << 1)   /* Done head write-back */
    106 #define I_SF   (1 << 2)   /* Start of frame */
    107 #define I_RD   (1 << 3)   /* Resume detect */
    108 #define I_UE   (1 << 4)   /* Unrecoverable error */
    109 #define I_FNO  (1 << 5)   /* Frame number overflow */
    110 #define I_RHSC (1 << 6)   /* Root hub status change */
    111 #define I_OC   (1 << 30)  /* Ownership change */
    112 #define I_MI   (1 << 31)  /* Master interrupt (any/all) */
    11365
    11466        /** HCCA pointer (see hw_struct hcca.h) */
    11567        ioport32_t hcca;
    116 #define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
    11768
    11869        /** Currently executed periodic endpoint */
    … …  
    13687        /** Frame time and max packet size for all transfers */
    13788        ioport32_t fm_interval;
    138 #define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
    139 #define FMI_FI_SHIFT (0)
    140 #define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
    141 #define FMI_FSMPS_SHIFT (16)
    142 #define FMI_TOGGLE_FLAG (1 << 31)
    14389
    14490        /** Bit times remaining in current frame */
    14591        const ioport32_t fm_remaining;
    146 #define FMR_FR_MASK FMI_FI_MASK
    147 #define FMR_FR_SHIFT FMI_FI_SHIFT
    148 #define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
    14992
    15093        /** Frame number */
    15194        const ioport32_t fm_number;
    152 #define FMN_NUMBER_MASK (0xffff)
    15395
    15496        /** Remaining bit time in frame to start periodic transfers */
    15597        ioport32_t periodic_start;
    156 #define PS_MASK 0x3fff
    157 #define PS_SHIFT 0
    15898
    15999        /** Threshold for starting LS transaction */
    160100        ioport32_t ls_threshold;
    161 #define LST_LST_MASK (0x7fff)
    162101
    163102        /** The first root hub control register */
    164103        ioport32_t rh_desc_a;
    165 /** Number of downstream ports, max 15 */
    166 #define RHDA_NDS_MASK  (0xff)
    167 /** Power switching mode: 0-global, 1-per port*/
    168 #define RHDA_PSM_FLAG  (1 << 8)
    169 /** No power switch: 1-power on, 0-use PSM*/
    170 #define RHDA_NPS_FLAG  (1 << 9)
    171 /** 1-Compound device, must be 0 */
    172 #define RHDA_DT_FLAG   (1 << 10)
    173 /** Over-current mode: 0-global, 1-per port */
    174 #define RHDA_OCPM_FLAG (1 << 11)
    175 /** OC control: 0-use OCPM, 1-OC off */
    176 #define RHDA_NOCP_FLAG (1 << 12)
    177 /** Power on to power good time */
    178 #define RHDA_POTPGT_SHIFT   24
    179104
    180105        /** The other root hub control register */
    181106        ioport32_t rh_desc_b;
    182 /** Device removable mask */
    183 #define RHDB_DR_SHIFT   0
    184 #define RHDB_DR_MASK    0xffffU
    185 /** Power control mask */
    186 #define RHDB_PCC_MASK   0xffffU
    187 #define RHDB_PCC_SHIFT  16
    188107
    189108        /** Root hub status register */
    190109        ioport32_t rh_status;
    191 /* read: 0,
    192  * write: 0-no effect,
    193  *        1-turn off port power for ports
    194  *        specified in PPCM(RHDB), or all ports,
    195  *        if power is set globally */
    196 #define RHS_LPS_FLAG  (1 <<  0)
    197 #define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
    198 /** Over-current indicator, if per-port: 0 */
    199 #define RHS_OCI_FLAG  (1 <<  1)
    200 
    201 /* read: 0-connect status change does not wake HC
    202  *       1-connect status change wakes HC
    203  * write: 1-set DRWE, 0-no effect */
    204 #define RHS_DRWE_FLAG (1 << 15)
    205 #define RHS_SET_DRWE RHS_DRWE_FLAG
    206 /* read: 0,
    207  * write: 0-no effect
    208  *        1-turn on port power for ports
    209  *        specified in PPCM(RHDB), or all ports,
    210  *        if power is set globally */
    211 #define RHS_LPSC_FLAG (1 << 16)
    212 #define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
    213 /** Over-current change indicator*/
    214 #define RHS_OCIC_FLAG (1 << 17)
    215 #define RHS_CLEAR_DRWE (1 << 31)
    216110
    217111        /** Root hub per port status */
    … …  
    249143} ohci_regs_t;
    250144
     145/*
     146 * ohci_regs_t.revision
     147 */
     148
     149#define R_REVISION_MASK (0x3f)
     150#define R_LEGACY_FLAG   (0x80)
     151
     152/*
     153 * ohci_regs_t.control
     154 */
     155 
     156/* Control-bulk service ratio */
     157#define C_CBSR_1_1  (0x0)
     158#define C_CBSR_1_2  (0x1)
     159#define C_CBSR_1_3  (0x2)
     160#define C_CBSR_1_4  (0x3)
     161#define C_CBSR_MASK (0x3)
     162#define C_CBSR_SHIFT 0
     163
     164#define C_PLE (1 << 2)   /* Periodic list enable */
     165#define C_IE  (1 << 3)   /* Isochronous enable */
     166#define C_CLE (1 << 4)   /* Control list enable */
     167#define C_BLE (1 << 5)   /* Bulk list enable */
     168
     169/* Host controller functional state */
     170#define C_HCFS_RESET       (0x0)
     171#define C_HCFS_RESUME      (0x1)
     172#define C_HCFS_OPERATIONAL (0x2)
     173#define C_HCFS_SUSPEND     (0x3)
     174#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
     175#define C_HCFS_SET(reg, value) \
     176do { \
     177        uint32_t r = OHCI_RD(reg); \
     178        r &= ~(0x3 << 6); \
     179        r |= (value & 0x3) << 6; \
     180        OHCI_WR(reg, r); \
     181} while (0)
     182
     183#define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
     184#define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
     185#define C_RWE (1 << 10)  /* Remote wakeup enable */
     186
     187/*
     188 * ohci_regs_t.command_status
     189 */
     190
     191#define CS_HCR (1 << 0)   /* Host controller reset */
     192#define CS_CLF (1 << 1)   /* Control list filled */
     193#define CS_BLF (1 << 2)   /* Bulk list filled */
     194#define CS_OCR (1 << 3)   /* Ownership change request */
     195#if 0
     196#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
     197#define CS_SOC_SHIFT (16)
    251198#endif
     199
     200/*
     201 * ohci_regs_t.interrupt_xxx
     202 */
     203
     204#define I_SO   (1 << 0)   /* Scheduling overrun */
     205#define I_WDH  (1 << 1)   /* Done head write-back */
     206#define I_SF   (1 << 2)   /* Start of frame */
     207#define I_RD   (1 << 3)   /* Resume detect */
     208#define I_UE   (1 << 4)   /* Unrecoverable error */
     209#define I_FNO  (1 << 5)   /* Frame number overflow */
     210#define I_RHSC (1 << 6)   /* Root hub status change */
     211#define I_OC   (1 << 30)  /* Ownership change */
     212#define I_MI   (1 << 31)  /* Master interrupt (any/all) */
     213
     214
     215/*
     216 * ohci_regs_t.hcca
     217 */
     218
     219#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
     220
     221/*
     222 * ohci_regs_t.fm_interval
     223 */
     224
     225#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
     226#define FMI_FI_SHIFT (0)
     227#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
     228#define FMI_FSMPS_SHIFT (16)
     229#define FMI_TOGGLE_FLAG (1 << 31)
     230
     231/*
     232 * ohci_regs_t.fm_remaining
     233 */
     234
     235#define FMR_FR_MASK FMI_FI_MASK
     236#define FMR_FR_SHIFT FMI_FI_SHIFT
     237#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
     238
     239/*
     240 * ohci_regs_t.fm_number
     241 */
     242
     243#define FMN_NUMBER_MASK (0xffff)
     244
     245/*
     246 * ohci_regs_t.periodic_start
     247 */
     248
     249#define PS_MASK 0x3fff
     250#define PS_SHIFT 0
     251
     252/*
     253 * ohci_regs_t.ls_threshold
     254 */
     255
     256#define LST_LST_MASK (0x7fff)
     257
     258/*
     259 * ohci_regs_t.rh_desc_a
     260 */
     261
     262/** Number of downstream ports, max 15 */
     263#define RHDA_NDS_MASK  (0xff)
     264/** Power switching mode: 0-global, 1-per port*/
     265#define RHDA_PSM_FLAG  (1 << 8)
     266/** No power switch: 1-power on, 0-use PSM*/
     267#define RHDA_NPS_FLAG  (1 << 9)
     268/** 1-Compound device, must be 0 */
     269#define RHDA_DT_FLAG   (1 << 10)
     270/** Over-current mode: 0-global, 1-per port */
     271#define RHDA_OCPM_FLAG (1 << 11)
     272/** OC control: 0-use OCPM, 1-OC off */
     273#define RHDA_NOCP_FLAG (1 << 12)
     274/** Power on to power good time */
     275#define RHDA_POTPGT_SHIFT   24
     276
     277/*
     278 * ohci_regs_t.rh_desc_b
     279 */
     280
     281/** Device removable mask */
     282#define RHDB_DR_SHIFT   0
     283#define RHDB_DR_MASK    0xffffU
     284
     285/** Power control mask */
     286#define RHDB_PCC_MASK   0xffffU
     287#define RHDB_PCC_SHIFT  16
     288
     289/*
     290 * ohci_regs_t.rh_status
     291 */
     292
     293/*
     294 * read: 0,
     295 * write: 0-no effect,
     296 *        1-turn off port power for ports
     297 *        specified in PPCM(RHDB), or all ports,
     298 *        if power is set globally
     299 */
     300#define RHS_LPS_FLAG  (1 <<  0)
     301#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
     302/** Over-current indicator, if per-port: 0 */
     303#define RHS_OCI_FLAG  (1 <<  1)
     304/*
     305 * read: 0-connect status change does not wake HC
     306 *       1-connect status change wakes HC
     307 * write: 1-set DRWE, 0-no effect
     308 */
     309#define RHS_DRWE_FLAG (1 << 15)
     310#define RHS_SET_DRWE RHS_DRWE_FLAG
     311/*
     312 * read: 0,
     313 * write: 0-no effect
     314 *        1-turn on port power for ports
     315 *        specified in PPCM(RHDB), or all ports,
     316 *        if power is set globally
     317 */
     318#define RHS_LPSC_FLAG (1 << 16)
     319#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
     320/** Over-current change indicator*/
     321#define RHS_OCIC_FLAG (1 << 17)
     322#define RHS_CLEAR_DRWE (1 << 31)
     323
     324#endif
     325
     326/*
     327 * ohci_regs_t.rh_port_status[x]
     328 */
     329
     330/** r: current connect status, w: 1-clear port enable, 0-N/S*/
     331#define RHPS_CCS_FLAG (1 << 0)
     332#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
     333/** r: port enable status, w: 1-set port enable, 0-N/S */
     334#define RHPS_PES_FLAG (1 << 1)
     335#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
     336/** r: port suspend status, w: 1-set port suspend, 0-N/S */
     337#define RHPS_PSS_FLAG (1 << 2)
     338#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
     339/** r: port over-current (if reports are per-port
     340 * w: 1-clear port suspend (start resume if suspened), 0-nothing
     341 */
     342#define RHPS_POCI_FLAG (1 << 3)
     343#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
     344/** r: port reset status, w: 1-set port reset, 0-N/S */
     345#define RHPS_PRS_FLAG (1 << 4)
     346#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
     347/** r: port power status, w: 1-set port power, 0-N/S */
     348#define RHPS_PPS_FLAG (1 << 8)
     349#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
     350/** r: low speed device attached, w: 1-clear port power, 0-N/S */
     351#define RHPS_LSDA_FLAG (1 << 9)
     352#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
     353/** connect status change WC */
     354#define RHPS_CSC_FLAG  (1 << 16)
     355/** port enable status change WC */
     356#define RHPS_PESC_FLAG (1 << 17)
     357/** port suspend status change WC */
     358#define RHPS_PSSC_FLAG (1 << 18)
     359/** port over-current change WC */
     360#define RHPS_OCIC_FLAG (1 << 19)
     361/** port reset status change WC */
     362#define RHPS_PRSC_FLAG (1 << 20)
     363#define RHPS_CHANGE_WC_MASK (0x1f0000)
    252364
    253365/**

  • uspace/drv/bus/usb/uhci/hc.c

    r4f8772d4 r904b1bc  
    531531            &instance->transfers_control_slow);
    532532
    533         /*FSBR, This feature is not needed (adds no benefit) and is supposedly
    534          * buggy on certain hw, enable at your own risk. */
     533        /*
     534         * FSBR, This feature is not needed (adds no benefit) and is supposedly
     535         * buggy on certain hw, enable at your own risk.
     536         */
    535537#ifdef FSBR
    536538        transfer_list_set_next(&instance->transfers_bulk_full,

  • uspace/drv/bus/usb/xhci/commands.h

    r4f8772d4 r904b1bc  
    7979        xhci_trb_ring_t trb_ring;
    8080
    81         fibril_mutex_t guard;           /**< Guard access to this structure. */
     81        /** Guard access to this structure. */
     82        fibril_mutex_t guard;
    8283        list_t cmd_list;
    8384
    84         xhci_cr_state_t state;          /**< Whether commands are allowed to be
    85                                              added. */
    86         fibril_condvar_t state_cv;      /**< For waiting on CR state change. */
     85        /** Whether commands are allowed to be added. */
     86        xhci_cr_state_t state;
     87        /** For waiting on CR state change. */
     88        fibril_condvar_t state_cv;
    8789
    88         fibril_condvar_t stopped_cv;    /**< For waiting on CR stopped event. */
     90        /** For waiting on CR stopped event. */
     91        fibril_condvar_t stopped_cv;
    8992} xhci_cmd_ring_t;
    9093
    … …  
    108111
    109112        /** Below are arguments of all commands mixed together.
    110          *  Be sure to know which command accepts what arguments. */
     113         *  Be sure to know which command accepts what arguments.
     114         */
    111115
    112116        uint32_t slot_id;

  • uspace/drv/nic/ne2k/dp8390.c

    r4f8772d4 r904b1bc  
    475475        size_t frames_count = 0;
    476476
    477         /* We may block sending in this loop - after so many received frames there
     477        /*
     478         * We may block sending in this loop - after so many received frames there
    478479         * must be some interrupt pending (for the frames not yet downloaded) and
    479          * we will continue in its handler. */
     480         * we will continue in its handler.
     481         */
    480482        while (frames_count < 16) {
    481483                //TODO: isn't some locking necessary here?

  • uspace/drv/nic/rtl8139/defs.h

    r4f8772d4 r904b1bc  
    280280/** Receiver control register values */
    281281enum rtl8139_rcr {
    282         RCR_ERTH_SHIFT = 24,       /**< Early Rx treshold part shift */
    283         RCR_ERTH_SIZE = 4,         /**< Early Rx treshold part size */
    284 
    285         RCR_MulERINT = 1 << 17,    /**< Multiple early interrupt select */
    286 
    287         /** Minimal error frame length (1 = 8B, 0 = 64B). If AER/AR is set, RER8
    288          * is "Don't care"
     282        /** Early Rx treshold part shift */
     283        RCR_ERTH_SHIFT = 24,
     284        /** Early Rx treshold part size */
     285        RCR_ERTH_SIZE = 4,
     286
     287        /** Multiple early interrupt select */
     288        RCR_MulERINT = 1 << 17,
     289
     290        /** Minimal error frame length (1 = 8B, 0 = 64B).
     291         * If AER/AR is set, RER8 is "Don't care"
    289292         */
    290293        RCR_RER8 = 1 << 16,
    291294
    292         RCR_RXFTH_SHIFT = 13,    /**< Rx FIFO treshold part shitf */
    293         RCR_RXFTH_SIZE  = 3,     /**< Rx FIFO treshold part size */
    294 
    295         RCR_RBLEN_SHIFT = 11,    /**< Rx buffer length part shift */
    296         RCR_RBLEN_SIZE  = 2,     /**< Rx buffer length part size */
    297 
    298         RCR_RBLEN_8k  = 0x00 << RCR_RBLEN_SHIFT,  /**< 8K + 16 byte rx buffer */
    299         RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT,  /**< 16K + 16 byte rx buffer */
    300         RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT,  /**< 32K + 16 byte rx buffer */
    301         RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT,  /**< 64K + 16 byte rx buffer */
    302 
    303         RCR_MXDMA_SHIFT = 8,             /**< Max DMA Burst Size part shift */
    304         RCR_MXDMA_SIZE  = 3,             /**< Max DMA Burst Size part size */
    305 
    306         RCR_WRAP              = 1 << 7,  /**< Rx buffer wrapped */
    307         RCR_ACCEPT_ERROR      = 1 << 5,  /**< Accept error frame */
    308         RCR_ACCEPT_RUNT       = 1 << 4,  /**< Accept Runt (8-64 bytes) frames */
    309         RCR_ACCEPT_BROADCAST  = 1 << 3,  /**< Accept broadcast */
    310         RCR_ACCEPT_MULTICAST  = 1 << 2,  /**< Accept multicast */
    311         RCR_ACCEPT_PHYS_MATCH = 1 << 1,  /**< Accept device MAC address match */
    312         RCR_ACCEPT_ALL_PHYS   = 1 << 0,  /**< Accept all frames with
    313                                           * phys. desticnation
    314                                                                           */
    315         RCR_ACCEPT_MASK = (1 << 6) - 1   /**< Mask of accept part */
     295        /** Rx FIFO treshold part shift */
     296        RCR_RXFTH_SHIFT = 13,
     297        /** Rx FIFO treshold part size */
     298        RCR_RXFTH_SIZE  = 3,
     299
     300        /** Rx buffer length part shift */
     301        RCR_RBLEN_SHIFT = 11,
     302        /** Rx buffer length part size */
     303        RCR_RBLEN_SIZE  = 2,
     304
     305        /** 8K + 16 byte rx buffer */
     306        RCR_RBLEN_8k  = 0x00 << RCR_RBLEN_SHIFT,
     307        /** 16K + 16 byte rx buffer */
     308        RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT,
     309        /** 32K + 16 byte rx buffer */
     310        RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT,
     311        /** 64K + 16 byte rx buffer */
     312        RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT,
     313
     314        /** Max DMA Burst Size part shift */
     315        RCR_MXDMA_SHIFT = 8,
     316        /** Max DMA Burst Size part size */
     317        RCR_MXDMA_SIZE  = 3,
     318
     319        /** Rx buffer wrapped */
     320        RCR_WRAP              = 1 << 7,
     321        /** Accept error frame */
     322        RCR_ACCEPT_ERROR      = 1 << 5,
     323        /** Accept Runt (8-64 bytes) frames */
     324        RCR_ACCEPT_RUNT       = 1 << 4,
     325        /** Accept broadcast */
     326        RCR_ACCEPT_BROADCAST  = 1 << 3,
     327        /** Accept multicast */
     328        RCR_ACCEPT_MULTICAST  = 1 << 2,
     329        /** Accept device MAC address match */
     330        RCR_ACCEPT_PHYS_MATCH = 1 << 1,
     331        /** Accept all frames with phys. destination */
     332        RCR_ACCEPT_ALL_PHYS   = 1 << 0,
     333        /** Mask of accept part */
     334        RCR_ACCEPT_MASK = (1 << 6) - 1
    316335};
    317336
    … …  
    320339enum rtl8139_cscr {
    321340        CS_Testfun       = (1 << 15),
    322         CS_LD            = (1 << 9),  /**< Low TPI link disable signal */
    323         CS_HEART_BEAT    = (1 << 8),  /**< Heart beat enable; 10Mbit mode only */
    324         CS_JABBER_ENABLE = (1 << 7),  /**< Enable jabber function */
     341        /** Low TPI link disable signal */
     342        CS_LD            = (1 << 9),
     343        /** Heart beat enable; 10Mbit mode only */
     344        CS_HEART_BEAT    = (1 << 8),
     345        /** Enable jabber function */
     346        CS_JABBER_ENABLE = (1 << 7),
    325347        CS_F_LINK100     = (1 << 6),
    326348        CS_F_CONNECT     = (1 << 5),
    327         CS_CON_STATUS    = (1 << 3),  /**< connection status:
    328                                        *   1 = valid, 0 = disconnected
    329                                                                    */
    330         CS_CON_STATUS_EN = (1 << 2),  /**< LED1 pin connection status indication */
    331         CS_PASS_SCR      = (1 << 0)   /**< Bypass Scramble  */
     349        /** connection status: 1 = valid, 0 = disconnected */
     350        CS_CON_STATUS    = (1 << 3),
     351        /** LED1 pin connection status indication */
     352        CS_CON_STATUS_EN = (1 << 2),
     353        /** Bypass Scramble */
     354        CS_PASS_SCR      = (1 << 0)
    332355};
    333356
    … …  
    360383/** Auto-negotiation advertisement register */
    361384enum rtl8139_anar {
    362         ANAR_NEXT_PAGE    = (1 << 15),  /**< Next page bit, 0 - primary capability
    363                                          *  1 - protocol specific
    364                                                                          */
    365         ANAR_ACK          = (1 << 14),  /**< Capability reception acknowledge */
    366         ANAR_REMOTE_FAULT = (1 << 13),  /**< Remote fault detection capability */
    367         ANAR_PAUSE        = (1 << 10),  /**< Symetric pause frame capability */
    368         ANAR_100T4        = (1 << 9),   /**< T4, not supported by the device */
    369         ANAR_100TX_FD     = (1 << 8),   /**< 100BASE_TX full duplex */
    370         ANAR_100TX_HD     = (1 << 7),   /**< 100BASE_TX half duplex */
    371         ANAR_10_FD        = (1 << 6),   /**< 10BASE_T full duplex */
    372         ANAR_10_HD        = (1 << 5),   /**< 10BASE_T half duplex */
    373         ANAR_SELECTOR     = 0x1         /**< Selector,
    374                                          *   CSMA/CD (0x1) supported only
    375                                                                          */
     385        /** Next page bit, 0 - primary capability, 1 - protocol specific */
     386        ANAR_NEXT_PAGE    = (1 << 15),
     387        /** Capability reception acknowledge */
     388        ANAR_ACK          = (1 << 14),
     389        /** Remote fault detection capability */
     390        ANAR_REMOTE_FAULT = (1 << 13),
     391        /** Symetric pause frame capability */
     392        ANAR_PAUSE        = (1 << 10),
     393        /** T4, not supported by the device */
     394        ANAR_100T4        = (1 << 9),
     395        /** 100BASE_TX full duplex */
     396        ANAR_100TX_FD     = (1 << 8),
     397        /** 100BASE_TX half duplex */
     398        ANAR_100TX_HD     = (1 << 7),
     399        /** 10BASE_T full duplex */
     400        ANAR_10_FD        = (1 << 6),
     401        /** 10BASE_T half duplex */
     402        ANAR_10_HD        = (1 << 5),
     403        /** Selector, CSMA/CD (0x1) supported only */
     404        ANAR_SELECTOR     = 0x1
    376405};
    377406
    … …  
    409438
    410439enum rtl8139_config4 {
    411         CONFIG4_RxFIFOAutoClr = (1 << 7),  /**< Automatic RxFIFO owerflow clear */
    412         CONFIG4_AnaOff        = (1 << 6),  /**< Analog poweroff */
    413         CONFIG4_LongWF        = (1 << 5),  /**< Long wakeup frame
    414                                             *   (2xCRC8 + 3xCRC16)
    415                                                                                 */
    416         CONFIG4_LWPME         = (1 << 4),  /**< LWAKE and PMEB assertion  */
    417         CONFIG4_LWPTN         = (1 << 2),  /**< LWake pattern */
    418         CONFIG4_PBWakeup      = (1 << 0)   /**< Preboot wakeup */
     440        /** Automatic RxFIFO owerflow clear */
     441        CONFIG4_RxFIFOAutoClr = (1 << 7),
     442        /** Analog poweroff */
     443        CONFIG4_AnaOff        = (1 << 6),
     444        /** Long wakeup frame (2xCRC8 + 3xCRC16) */
     445        CONFIG4_LongWF        = (1 << 5),
     446        /** LWAKE and PMEB assertion */
     447        CONFIG4_LWPME         = (1 << 4),
     448        /** LWake pattern */
     449        CONFIG4_LWPTN         = (1 << 2),
     450        /** Preboot wakeup */
     451        CONFIG4_PBWakeup      = (1 << 0)
    419452};
    420453
    … …  
    438471
    439472enum rtl8139_tcr_bits {
    440         HWVERID_A_SHIFT = 26,           /**< HW version id, part A shift */
    441         HWVERID_A_SIZE  = 5,            /**< HW version id, part A bit size */
    442         HWVERID_A_MASK  = (1 << 5) - 1, /**< HW version id, part A mask */
    443 
    444         IFG_SHIFT = 24,           /**< The interframe gap time setting shift */
    445         IFG_SIZE  = 2,            /**< The interframe gap time setting bit size */
    446 
    447         HWVERID_B_SHIFT = 22,           /**< HW version id, part B shift */
    448         HWVERID_B_SIZE  = 2,            /**< HW version id, part B bit size */
    449         HWVERID_B_MASK  = (1 << 2) - 1, /**< HW version id, part B mask */
    450 
    451         LOOPBACK_SHIFT  = 17,           /**< Loopback mode shift */
    452         LOOPBACK_SIZE   = 2,            /**< Loopback mode size
    453                                           *  00 = normal, 11 = loopback
    454                                                                           */
    455 
    456         APPEND_CRC = 1 << 16,        /**< Append CRC at the end of a frame */
    457 
    458         MXTxDMA_SHIFT = 8,  /**< Max. DMA Burst per TxDMA shift, burst = 16^value */
    459         MXTxDMA_SIZE  = 3,  /**< Max. DMA Burst per TxDMA bit size */
    460 
    461         TX_RETRY_COUNT_SHIFT = 4,            /**< Retries before aborting shift */
    462         TX_RETRY_COUNT_SIZE  = 4,            /**< Retries before aborting size */
    463 
    464         CLEAR_ABORT = 1 << 0    /**< Retransmit aborted frame at the last
    465                                   *  transmitted descriptor
    466                                                           */
     473        /** HW version id, part A shift */
     474        HWVERID_A_SHIFT = 26,
     475        /** HW version id, part A bit size */
     476        HWVERID_A_SIZE  = 5,
     477        /** HW version id, part A mask */
     478        HWVERID_A_MASK  = (1 << 5) - 1,
     479
     480        /** The interframe gap time setting shift */
     481        IFG_SHIFT = 24,
     482        /** The interframe gap time setting bit size */
     483        IFG_SIZE  = 2,
     484
     485        /** HW version id, part B shift */
     486        HWVERID_B_SHIFT = 22,
     487        /** HW version id, part B bit size */
     488        HWVERID_B_SIZE  = 2,
     489        /** HW version id, part B mask */
     490        HWVERID_B_MASK  = (1 << 2) - 1,
     491
     492        /** Loopback mode shift */
     493        LOOPBACK_SHIFT  = 17,
     494        /** Loopback mode size. 00 = normal, 11 = loopback */
     495        LOOPBACK_SIZE   = 2,
     496
     497        /** Append CRC at the end of a frame */
     498        APPEND_CRC = 1 << 16,
     499
     500        /** Max. DMA Burst per TxDMA shift, burst = 16^value */
     501        MXTxDMA_SHIFT = 8,
     502        /** Max. DMA Burst per TxDMA bit size */
     503        MXTxDMA_SIZE  = 3,
     504
     505        /** Retries before aborting shift */
     506        TX_RETRY_COUNT_SHIFT = 4,
     507        /** Retries before aborting size */
     508        TX_RETRY_COUNT_SIZE  = 4,
     509
     510        /** Retransmit aborted frame at the last transmitted descriptor */
     511        CLEAR_ABORT = 1 << 0
    467512};
    468513
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