Changeset 8f9d70b in mainline for boot/arch/arm32/include
- Timestamp:
- 2013-03-24T14:55:36Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0dfa93b0
- Parents:
- 119b46e
- Location:
- boot/arch/arm32/include
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/include/arch.h
r119b46e r8f9d70b 46 46 #elif defined MACHINE_beaglebone 47 47 #define BOOT_BASE 0x80000000 48 #elif defined MACHINE_raspberrypi 49 #define BOOT_BASE 0x00008000 48 50 #else 49 51 #define BOOT_BASE 0x00000000 -
boot/arch/arm32/include/main.h
r119b46e r8f9d70b 75 75 #define ICP_SCONS_ADDR 0x16000000 76 76 77 /** Raspberry PI serial console registers */ 78 #define BCM2835_UART0_BASE 0x20201000 79 #define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00) 80 #define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18) 81 #define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20) 82 #define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24) 83 #define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28) 84 #define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C) 85 #define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30) 86 #define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44) 87 88 #define BCM2835_UART0_FR_TXFF (1 << 5) 89 #define BCM2835_UART0_LCRH_FEN (1 << 4) 90 #define BCM2835_UART0_LCRH_WL8 ((1 << 5) | (1 << 6)) 91 #define BCM2835_UART0_CR_UARTEN (1 << 0) 92 #define BCM2835_UART0_CR_TXE (1 << 8) 93 #define BCM2835_UART0_CR_RXE (1 << 9) 94 95 96 77 97 extern void bootstrap(void); 78 98 -
boot/arch/arm32/include/mm.h
r119b46e r8f9d70b 68 68 #define AM335x_RAM_END 0xC0000000 69 69 70 /** Start of ram memory on BCM2835 */ 71 #define BCM2835_RAM_START 0 72 /** End of ram memory on BCM2835 */ 73 #define BCM2835_RAM_END 0x20000000 70 74 71 75 /* Page table level 0 entry - "section" format is used
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