Changeset 8df5f20 in mainline for kernel/arch/sparc64/include
- Timestamp:
- 2019-02-11T14:56:26Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4805495
- Parents:
- 391996b
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2019-02-01 23:26:21)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2019-02-11 14:56:26)
- Location:
- kernel/arch/sparc64/include/arch
- Files:
-
- 8 edited
-
asm.h (modified) (36 diffs)
-
barrier.h (modified) (2 diffs)
-
cycle.h (modified) (1 diff)
-
istate.h (modified) (2 diffs)
-
mm/sun4u/tlb.h (modified) (33 diffs)
-
mm/sun4v/tlb.h (modified) (6 diffs)
-
sun4u/asm.h (modified) (1 diff)
-
sun4u/cpu.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/arch/asm.h
r391996b r8df5f20 44 44 #include <trace.h> 45 45 46 NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)46 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) 47 47 { 48 48 *port = v; … … 50 50 } 51 51 52 NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)52 _NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) 53 53 { 54 54 *port = v; … … 56 56 } 57 57 58 NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)58 _NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) 59 59 { 60 60 *port = v; … … 62 62 } 63 63 64 NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)64 _NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) 65 65 { 66 66 uint8_t rv = *port; … … 69 69 } 70 70 71 NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)71 _NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) 72 72 { 73 73 uint16_t rv = *port; … … 76 76 } 77 77 78 NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)78 _NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) 79 79 { 80 80 uint32_t rv = *port; … … 88 88 * 89 89 */ 90 NO_TRACE static inline uint64_t pstate_read(void)90 _NO_TRACE static inline uint64_t pstate_read(void) 91 91 { 92 92 uint64_t v; … … 105 105 * 106 106 */ 107 NO_TRACE static inline void pstate_write(uint64_t v)107 _NO_TRACE static inline void pstate_write(uint64_t v) 108 108 { 109 109 asm volatile ( … … 119 119 * 120 120 */ 121 NO_TRACE static inline uint64_t tick_compare_read(void)121 _NO_TRACE static inline uint64_t tick_compare_read(void) 122 122 { 123 123 uint64_t v; … … 136 136 * 137 137 */ 138 NO_TRACE static inline void tick_compare_write(uint64_t v)138 _NO_TRACE static inline void tick_compare_write(uint64_t v) 139 139 { 140 140 asm volatile ( … … 150 150 * 151 151 */ 152 NO_TRACE static inline uint64_t stick_compare_read(void)152 _NO_TRACE static inline uint64_t stick_compare_read(void) 153 153 { 154 154 uint64_t v; … … 167 167 * 168 168 */ 169 NO_TRACE static inline void stick_compare_write(uint64_t v)169 _NO_TRACE static inline void stick_compare_write(uint64_t v) 170 170 { 171 171 asm volatile ( … … 181 181 * 182 182 */ 183 NO_TRACE static inline uint64_t tick_read(void)183 _NO_TRACE static inline uint64_t tick_read(void) 184 184 { 185 185 uint64_t v; … … 198 198 * 199 199 */ 200 NO_TRACE static inline void tick_write(uint64_t v)200 _NO_TRACE static inline void tick_write(uint64_t v) 201 201 { 202 202 asm volatile ( … … 212 212 * 213 213 */ 214 NO_TRACE static inline uint64_t fprs_read(void)214 _NO_TRACE static inline uint64_t fprs_read(void) 215 215 { 216 216 uint64_t v; … … 229 229 * 230 230 */ 231 NO_TRACE static inline void fprs_write(uint64_t v)231 _NO_TRACE static inline void fprs_write(uint64_t v) 232 232 { 233 233 asm volatile ( … … 243 243 * 244 244 */ 245 NO_TRACE static inline uint64_t softint_read(void)245 _NO_TRACE static inline uint64_t softint_read(void) 246 246 { 247 247 uint64_t v; … … 260 260 * 261 261 */ 262 NO_TRACE static inline void softint_write(uint64_t v)262 _NO_TRACE static inline void softint_write(uint64_t v) 263 263 { 264 264 asm volatile ( … … 276 276 * 277 277 */ 278 NO_TRACE static inline void clear_softint_write(uint64_t v)278 _NO_TRACE static inline void clear_softint_write(uint64_t v) 279 279 { 280 280 asm volatile ( … … 292 292 * 293 293 */ 294 NO_TRACE static inline void set_softint_write(uint64_t v)294 _NO_TRACE static inline void set_softint_write(uint64_t v) 295 295 { 296 296 asm volatile ( … … 309 309 * 310 310 */ 311 NO_TRACE static inline ipl_t interrupts_enable(void)311 _NO_TRACE static inline ipl_t interrupts_enable(void) 312 312 { 313 313 pstate_reg_t pstate; … … 329 329 * 330 330 */ 331 NO_TRACE static inline ipl_t interrupts_disable(void)331 _NO_TRACE static inline ipl_t interrupts_disable(void) 332 332 { 333 333 pstate_reg_t pstate; … … 348 348 * 349 349 */ 350 NO_TRACE static inline void interrupts_restore(ipl_t ipl)350 _NO_TRACE static inline void interrupts_restore(ipl_t ipl) 351 351 { 352 352 pstate_reg_t pstate; … … 364 364 * 365 365 */ 366 NO_TRACE static inline ipl_t interrupts_read(void)366 _NO_TRACE static inline ipl_t interrupts_read(void) 367 367 { 368 368 return (ipl_t) pstate_read(); … … 374 374 * 375 375 */ 376 NO_TRACE static inline bool interrupts_disabled(void)376 _NO_TRACE static inline bool interrupts_disabled(void) 377 377 { 378 378 pstate_reg_t pstate; … … 389 389 * 390 390 */ 391 NO_TRACE static inline uintptr_t get_stack_base(void)391 _NO_TRACE static inline uintptr_t get_stack_base(void) 392 392 { 393 393 uintptr_t unbiased_sp; … … 407 407 * 408 408 */ 409 NO_TRACE static inline uint64_t ver_read(void)409 _NO_TRACE static inline uint64_t ver_read(void) 410 410 { 411 411 uint64_t v; … … 424 424 * 425 425 */ 426 NO_TRACE static inline uint64_t tpc_read(void)426 _NO_TRACE static inline uint64_t tpc_read(void) 427 427 { 428 428 uint64_t v; … … 441 441 * 442 442 */ 443 NO_TRACE static inline uint64_t tl_read(void)443 _NO_TRACE static inline uint64_t tl_read(void) 444 444 { 445 445 uint64_t v; … … 458 458 * 459 459 */ 460 NO_TRACE static inline uint64_t tba_read(void)460 _NO_TRACE static inline uint64_t tba_read(void) 461 461 { 462 462 uint64_t v; … … 475 475 * 476 476 */ 477 NO_TRACE static inline void tba_write(uint64_t v)477 _NO_TRACE static inline void tba_write(uint64_t v) 478 478 { 479 479 asm volatile ( … … 493 493 * 494 494 */ 495 NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)495 _NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) 496 496 { 497 497 uint64_t v; … … 514 514 * 515 515 */ 516 NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)516 _NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) 517 517 { 518 518 asm volatile ( … … 526 526 527 527 /** Flush all valid register windows to memory. */ 528 NO_TRACE static inline void flushw(void)528 _NO_TRACE static inline void flushw(void) 529 529 { 530 530 asm volatile ("flushw\n"); … … 532 532 533 533 /** Switch to nucleus by setting TL to 1. */ 534 NO_TRACE static inline void nucleus_enter(void)534 _NO_TRACE static inline void nucleus_enter(void) 535 535 { 536 536 asm volatile ("wrpr %g0, 1, %tl\n"); … … 538 538 539 539 /** Switch from nucleus by setting TL to 0. */ 540 NO_TRACE static inline void nucleus_leave(void)540 _NO_TRACE static inline void nucleus_leave(void) 541 541 { 542 542 asm volatile ("wrpr %g0, %g0, %tl\n"); -
kernel/arch/sparc64/include/arch/barrier.h
r391996b r8df5f20 39 39 40 40 /** Flush Instruction pipeline. */ 41 NO_TRACE static inline void flush_pipeline(void)41 _NO_TRACE static inline void flush_pipeline(void) 42 42 { 43 43 unsigned long pc; … … 62 62 63 63 /** Memory Barrier instruction. */ 64 NO_TRACE static inline void membar(void)64 _NO_TRACE static inline void membar(void) 65 65 { 66 66 asm volatile ( -
kernel/arch/sparc64/include/arch/cycle.h
r391996b r8df5f20 39 39 #include <trace.h> 40 40 41 NO_TRACE static inline uint64_t get_cycle(void)41 _NO_TRACE static inline uint64_t get_cycle(void) 42 42 { 43 43 return tick_read(); -
kernel/arch/sparc64/include/arch/istate.h
r391996b r8df5f20 51 51 #endif /* KERNEL */ 52 52 53 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,53 _NO_TRACE static inline void istate_set_retaddr(istate_t *istate, 54 54 uintptr_t retaddr) 55 55 { … … 57 57 } 58 58 59 NO_TRACE static inline int istate_from_uspace(istate_t *istate)59 _NO_TRACE static inline int istate_from_uspace(istate_t *istate) 60 60 { 61 61 return !(istate->tstate & TSTATE_PRIV_BIT); 62 62 } 63 63 64 NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)64 _NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate) 65 65 { 66 66 return istate->tpc; 67 67 } 68 68 69 NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)69 _NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate) 70 70 { 71 71 /* TODO */ -
kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
r391996b r8df5f20 243 243 * Determine the number of entries in the DMMU's small TLB. 244 244 */ 245 NO_TRACE static inline uint16_t tlb_dsmall_size(void)245 _NO_TRACE static inline uint16_t tlb_dsmall_size(void) 246 246 { 247 247 return 16; … … 251 251 * Determine the number of entries in each DMMU's big TLB. 252 252 */ 253 NO_TRACE static inline uint16_t tlb_dbig_size(void)253 _NO_TRACE static inline uint16_t tlb_dbig_size(void) 254 254 { 255 255 return 512; … … 259 259 * Determine the number of entries in the IMMU's small TLB. 260 260 */ 261 NO_TRACE static inline uint16_t tlb_ismall_size(void)261 _NO_TRACE static inline uint16_t tlb_ismall_size(void) 262 262 { 263 263 return 16; … … 267 267 * Determine the number of entries in the IMMU's big TLB. 268 268 */ 269 NO_TRACE static inline uint16_t tlb_ibig_size(void)269 _NO_TRACE static inline uint16_t tlb_ibig_size(void) 270 270 { 271 271 if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) … … 281 281 * @return Current value of Primary Context Register. 282 282 */ 283 NO_TRACE static inline uint64_t mmu_primary_context_read(void)283 _NO_TRACE static inline uint64_t mmu_primary_context_read(void) 284 284 { 285 285 return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); … … 290 290 * @param v New value of Primary Context Register. 291 291 */ 292 NO_TRACE static inline void mmu_primary_context_write(uint64_t v)292 _NO_TRACE static inline void mmu_primary_context_write(uint64_t v) 293 293 { 294 294 asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); … … 300 300 * @return Current value of Secondary Context Register. 301 301 */ 302 NO_TRACE static inline uint64_t mmu_secondary_context_read(void)302 _NO_TRACE static inline uint64_t mmu_secondary_context_read(void) 303 303 { 304 304 return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); … … 309 309 * @param v New value of Primary Context Register. 310 310 */ 311 NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)311 _NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) 312 312 { 313 313 asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); … … 324 324 * Register. 325 325 */ 326 NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)326 _NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry) 327 327 { 328 328 itlb_data_access_addr_t reg; … … 338 338 * @param value Value to be written. 339 339 */ 340 NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)340 _NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value) 341 341 { 342 342 itlb_data_access_addr_t reg; … … 355 355 * Register. 356 356 */ 357 NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)357 _NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry) 358 358 { 359 359 dtlb_data_access_addr_t reg; … … 369 369 * @param value Value to be written. 370 370 */ 371 NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)371 _NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value) 372 372 { 373 373 dtlb_data_access_addr_t reg; … … 385 385 * @return Current value of specified IMMU TLB Tag Read Register. 386 386 */ 387 NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)387 _NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry) 388 388 { 389 389 itlb_tag_read_addr_t tag; … … 400 400 * @return Current value of specified DMMU TLB Tag Read Register. 401 401 */ 402 NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)402 _NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry) 403 403 { 404 404 dtlb_tag_read_addr_t tag; … … 419 419 * Register. 420 420 */ 421 NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)421 _NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry) 422 422 { 423 423 itlb_data_access_addr_t reg; … … 434 434 * @param value Value to be written. 435 435 */ 436 NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,436 _NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry, 437 437 uint64_t value) 438 438 { … … 454 454 * Register. 455 455 */ 456 NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)456 _NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) 457 457 { 458 458 dtlb_data_access_addr_t reg; … … 470 470 * @param value Value to be written. 471 471 */ 472 NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,472 _NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry, 473 473 uint64_t value) 474 474 { … … 489 489 * @return Current value of specified IMMU TLB Tag Read Register. 490 490 */ 491 NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)491 _NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) 492 492 { 493 493 itlb_tag_read_addr_t tag; … … 506 506 * @return Current value of specified DMMU TLB Tag Read Register. 507 507 */ 508 NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)508 _NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) 509 509 { 510 510 dtlb_tag_read_addr_t tag; … … 522 522 * @param v Value to be written. 523 523 */ 524 NO_TRACE static inline void itlb_tag_access_write(uint64_t v)524 _NO_TRACE static inline void itlb_tag_access_write(uint64_t v) 525 525 { 526 526 asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); … … 532 532 * @return Current value of IMMU TLB Tag Access Register. 533 533 */ 534 NO_TRACE static inline uint64_t itlb_tag_access_read(void)534 _NO_TRACE static inline uint64_t itlb_tag_access_read(void) 535 535 { 536 536 return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); … … 541 541 * @param v Value to be written. 542 542 */ 543 NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)543 _NO_TRACE static inline void dtlb_tag_access_write(uint64_t v) 544 544 { 545 545 asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); … … 551 551 * @return Current value of DMMU TLB Tag Access Register. 552 552 */ 553 NO_TRACE static inline uint64_t dtlb_tag_access_read(void)553 _NO_TRACE static inline uint64_t dtlb_tag_access_read(void) 554 554 { 555 555 return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); … … 560 560 * @param v Value to be written. 561 561 */ 562 NO_TRACE static inline void itlb_data_in_write(uint64_t v)562 _NO_TRACE static inline void itlb_data_in_write(uint64_t v) 563 563 { 564 564 asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); … … 570 570 * @param v Value to be written. 571 571 */ 572 NO_TRACE static inline void dtlb_data_in_write(uint64_t v)572 _NO_TRACE static inline void dtlb_data_in_write(uint64_t v) 573 573 { 574 574 asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); … … 580 580 * @return Current content of I-SFSR register. 581 581 */ 582 NO_TRACE static inline uint64_t itlb_sfsr_read(void)582 _NO_TRACE static inline uint64_t itlb_sfsr_read(void) 583 583 { 584 584 return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); … … 589 589 * @param v New value of I-SFSR register. 590 590 */ 591 NO_TRACE static inline void itlb_sfsr_write(uint64_t v)591 _NO_TRACE static inline void itlb_sfsr_write(uint64_t v) 592 592 { 593 593 asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); … … 599 599 * @return Current content of D-SFSR register. 600 600 */ 601 NO_TRACE static inline uint64_t dtlb_sfsr_read(void)601 _NO_TRACE static inline uint64_t dtlb_sfsr_read(void) 602 602 { 603 603 return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); … … 608 608 * @param v New value of D-SFSR register. 609 609 */ 610 NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)610 _NO_TRACE static inline void dtlb_sfsr_write(uint64_t v) 611 611 { 612 612 asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); … … 618 618 * @return Current content of D-SFAR register. 619 619 */ 620 NO_TRACE static inline uint64_t dtlb_sfar_read(void)620 _NO_TRACE static inline uint64_t dtlb_sfar_read(void) 621 621 { 622 622 return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); … … 631 631 * @param page Address which is on the page to be demapped. 632 632 */ 633 NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)633 _NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page) 634 634 { 635 635 tlb_demap_addr_t da; … … 657 657 * @param page Address which is on the page to be demapped. 658 658 */ 659 NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)659 _NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) 660 660 { 661 661 tlb_demap_addr_t da; -
kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h
r391996b r8df5f20 88 88 * @return Current value of Primary Context Register. 89 89 */ 90 NO_TRACE static inline uint64_t mmu_primary_context_read(void)90 _NO_TRACE static inline uint64_t mmu_primary_context_read(void) 91 91 { 92 92 return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); … … 97 97 * @param v New value of Primary Context Register. 98 98 */ 99 NO_TRACE static inline void mmu_primary_context_write(uint64_t v)99 _NO_TRACE static inline void mmu_primary_context_write(uint64_t v) 100 100 { 101 101 asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); … … 106 106 * @return Current value of Secondary Context Register. 107 107 */ 108 NO_TRACE static inline uint64_t mmu_secondary_context_read(void)108 _NO_TRACE static inline uint64_t mmu_secondary_context_read(void) 109 109 { 110 110 return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); … … 115 115 * @param v New value of Secondary Context Register. 116 116 */ 117 NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)117 _NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) 118 118 { 119 119 asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); … … 126 126 * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both 127 127 */ 128 NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag)128 _NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) 129 129 { 130 130 __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); … … 138 138 * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both 139 139 */ 140 NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag)140 _NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) 141 141 { 142 142 __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); -
kernel/arch/sparc64/include/arch/sun4u/asm.h
r391996b r8df5f20 43 43 * 44 44 */ 45 NO_TRACE static inline uint64_t ver_read(void)45 _NO_TRACE static inline uint64_t ver_read(void) 46 46 { 47 47 uint64_t v; -
kernel/arch/sparc64/include/arch/sun4u/cpu.h
r391996b r8df5f20 76 76 * 77 77 */ 78 NO_TRACE static inline uint32_t read_mid(void)78 _NO_TRACE static inline uint32_t read_mid(void) 79 79 { 80 80 uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
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