Changeset 8d2760f in mainline for kernel/genarch/src/kbd

Timestamp:

2008-11-29T20:24:47Z (17 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

57e76cb

Parents:

dfd77382

Message:

Add additional members to the irq_t structure so that an interrupt-driven driver
does not need to know how to clear the level interrupt. The z8530 was modified
in this way and is much more generic. The ns16550 driver has also been modified,
but awaits testing. The sparc64 interrupt mapping and dispatch code is now using
the new info and calls the clear-interrupt-routine itself.

Location:

kernel/genarch/src/kbd

Files:

• ns16550.c (modified) (2 diffs)
• z8530.c (modified) (5 diffs)

kernel/genarch/src/kbd/ns16550.c

@@ -108 +108 @@
 /** Initialize ns16550.
  *
- * @param devno Device number.
- * @param inr Interrupt number.
- * @param vaddr Virtual address of device's registers.
- */
-void ns16550_init(devno_t devno, inr_t inr, ioport_t port)
+ * @param devno         Device number.
+ * @param port          Virtual/IO address of device's registers.
+ * @param inr           Interrupt number.
+ * @param cir           Clear interrupt function.
+ * @param cir_arg       First argument to cir.
+ */
+void
+ns16550_init(devno_t devno, ioport_t port, inr_t inr, cir_t cir, void *cir_arg)
 {
         chardev_initialize("ns16550_kbd", &kbrd, &ops);
@@ -125 +128 @@
         ns16550_irq.claim = ns16550_claim;
         ns16550_irq.handler = ns16550_irq_handler;
+        ns16550_irq.cir = cir;
+        ns16550_irq.cir_arg = cir_arg;
         irq_register(&ns16550_irq);
         

kernel/genarch/src/kbd/z8530.c

@@ -44 +44 @@
 #include <arch/interrupt.h>
 #include <arch/drivers/kbd.h>
-#include <arch/drivers/fhc.h>
 #include <cpu.h>
 #include <arch/asm.h>
@@ -84 +83 @@
         z8530_write_a(&z8530, WR0, WR0_TX_IP_RST);
 
-        z8530_write_a(&z8530, WR1, WR1_IARCSC);         /* interrupt on all characters */
+        /* interrupt on all characters */
+        z8530_write_a(&z8530, WR1, WR1_IARCSC);
 
         /* 8 bits per character and enable receiver */
         z8530_write_a(&z8530, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
         
-        z8530_write_a(&z8530, WR9, WR9_MIE);            /* Master Interrupt Enable. */
+        /* Master Interrupt Enable. */
+        z8530_write_a(&z8530, WR9, WR9_MIE);
         
         spinlock_lock(&z8530_irq.lock);
@@ -109 +110 @@
 
 /** Initialize z8530. */
-void z8530_init(devno_t devno, inr_t inr, uintptr_t vaddr)
+void
+z8530_init(devno_t devno, uintptr_t vaddr, inr_t inr, cir_t cir, void *cir_arg)
 {
         chardev_initialize("z8530_kbd", &kbrd, &ops);
@@ -122 +124 @@
         z8530_irq.claim = z8530_claim;
         z8530_irq.handler = z8530_irq_handler;
+        z8530_irq.cir = cir;
+        z8530_irq.cir_arg = cir_arg;
         irq_register(&z8530_irq);
 
@@ -198 +202 @@
 void z8530_irq_handler(irq_t *irq, void *arg, ...)
 {
-        /*
-         * So far, we know we got this interrupt through the FHC.
-         * Since we don't have enough documentation about the FHC
-         * and because the interrupt looks like level sensitive,
-         * we cannot handle it by scheduling one of the level
-         * interrupt traps. Process the interrupt directly.
-         */
         if (irq->notif_cfg.notify && irq->notif_cfg.answerbox)
                 ipc_irq_send_notif(irq);
         else
                 z8530_interrupt();
-        fhc_clear_interrupt(central_fhc, irq->inr);
 }