Changeset 8c2214e in mainline for kernel/arch/sparc64/src/mm


Ignore:
Timestamp:
2010-02-20T20:29:27Z (16 years ago)
Author:
Pavel Rimsky <pavel@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f516bc2
Parents:
e0cb57b
Message:

Cleanup and merge of the TSB code.

Location:
kernel/arch/sparc64/src/mm
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/mm/sun4u/tlb.c

    re0cb57b r8c2214e  
    476476}
    477477
    478 void dump_sfsr_and_sfar(void)
     478void describe_dmmu_fault(void)
    479479{
    480480        tlb_sfsr_reg_t sfsr;
    … …  
    499499}
    500500
     501void dump_sfsr_and_sfar(void)
     502{
     503        tlb_sfsr_reg_t sfsr;
     504        uintptr_t sfar;
     505
     506        sfsr.value = dtlb_sfsr_read();
     507        sfar = dtlb_sfar_read();
     508       
     509#if defined (US)
     510        printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
     511            "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
     512            sfsr.ow, sfsr.fv);
     513#elif defined (US3)
     514        printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
     515            "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
     516            sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
     517#endif
     518           
     519        printf("DTLB SFAR: address=%p\n", sfar);
     520       
     521        dtlb_sfsr_write(0);
     522}
     523
    501524#if defined (US)
    502525/** Invalidate all unlocked ITLB and DTLB entries. */

  • kernel/arch/sparc64/src/mm/sun4v/as.c

    re0cb57b r8c2214e  
    11/*
    22 * Copyright (c) 2006 Jakub Jermar
     3 * Copyright (c) 2009 Pavel Rimsky
    34 * All rights reserved.
    45 *
    … …  
    3435
    3536#include <arch/mm/as.h>
     37#include <arch/mm/pagesize.h>
    3638#include <arch/mm/tlb.h>
    3739#include <genarch/mm/page_ht.h>
    … …  
    3941#include <debug.h>
    4042#include <config.h>
     43#include <arch/sun4v/hypercall.h>
    4144
    4245#ifdef CONFIG_TSB
    … …  
    8689{
    8790#ifdef CONFIG_TSB
    88         count_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
     91        size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
    8992        frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
    9093        return cnt;
    … …  
    112115{
    113116        mmu_secondary_context_write(as->asid);
     117#ifdef CONFIG_TSB       
     118        uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
     119
     120        ASSERT(as->arch.tsb_description.tsb_base);
     121        uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
     122               
     123        if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
     124                /*
     125                 * TSBs were allocated from memory not covered
     126                 * by the locked 4M kernel DTLB entry. We need
     127                 * to map both TSBs explicitly.
     128                 */
     129                mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
     130                dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
     131        }
     132
     133        __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description)));
     134       
     135#endif
    114136}
    115137
    … …  
    134156        uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
    135157
    136         ASSERT(as->arch.itsb && as->arch.dtsb);
     158        ASSERT(as->arch.tsb_description.tsb_base);
    137159
    138         uintptr_t tsb = (uintptr_t) as->arch.itsb;
     160        uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
    139161               
    140162        if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
    … …  
    144166                 * to demap the entry installed by as_install_arch().
    145167                 */
    146                 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
     168                __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB);
    147169        }
    148170#endif

  • kernel/arch/sparc64/src/mm/sun4v/tsb.c

    re0cb57b r8c2214e  
    11/*
    22 * Copyright (c) 2006 Jakub Jermar
     3 * Copyright (c) 2009 Pavel Rimsky
    34 * All rights reserved.
    45 *
    … …  
    3435
    3536#include <arch/mm/tsb.h>
     37#include <arch/mm/pagesize.h>
    3638#include <arch/mm/tlb.h>
    3739#include <arch/mm/page.h>
    … …  
    4951 * portions of both TSBs are invalidated at a time.
    5052 *
    51  * @param as Address space.
    52  * @param page First page to invalidate in TSB.
    53  * @param pages Number of pages to invalidate. Value of (size_t) -1 means the
    54  *      whole TSB.
     53 * @param as    Address space.
     54 * @param page  First page to invalidate in TSB.
     55 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
     56 *              whole TSB.
    5557 */
    5658void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
    5759{
    58         size_t i0;
    59         size_t i;
     60        size_t i0, i;
    6061        size_t cnt;
    6162       
    62         ASSERT(as->arch.itsb && as->arch.dtsb);
     63        ASSERT(as->arch.tsb_description.tsb_base);
    6364       
    6465        i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    65         ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
     66        ASSERT(i0 < TSB_ENTRY_COUNT);
    6667
    67         if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
    68                 cnt = ITSB_ENTRY_COUNT;
     68        if (pages == (size_t) - 1 || (pages) > TSB_ENTRY_COUNT)
     69                cnt = TSB_ENTRY_COUNT;
    6970        else
    70                 cnt = pages * 2;
     71                cnt = pages;
    7172       
    7273        for (i = 0; i < cnt; i++) {
    73                 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
    74                     true;
    75                 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
    76                     true;
     74                ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[
     75                        (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
    7776        }
    7877}
    … …  
    8180 *
    8281 * @param t     Software PTE.
    83  * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
    8482 */
    85 void itsb_pte_copy(pte_t *t, size_t index)
     83void itsb_pte_copy(pte_t *t)
    8684{
    87 #if 0
    8885        as_t *as;
    8986        tsb_entry_t *tsb;
    9087        size_t entry;
    9188
    92         ASSERT(index <= 1);
    93        
    9489        as = t->as;
    95         entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    96         ASSERT(entry < ITSB_ENTRY_COUNT);
    97         tsb = &as->arch.itsb[entry];
     90        entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
     91        ASSERT(entry < TSB_ENTRY_COUNT);
     92        tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
    9893
    9994        /*
    … …  
    10398         */
    10499
    105         tsb->tag.invalid = true;        /* invalidate the entry
    106                                          * (tag target has this
    107                                          * set to 0) */
     100        tsb->data.v = false;
    108101
    109102        write_barrier();
    110103
    111         tsb->tag.context = as->asid;
    112         /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
    113104        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
     105
    114106        tsb->data.value = 0;
     107        tsb->data.nfo = false;
     108        tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
     109        tsb->data.ie = false;
     110        tsb->data.e = false;
     111        tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
     112        tsb->data.cv = false;
     113        tsb->data.p = t->k;     /* p as privileged, k as kernel */
     114        tsb->data.x = true;
     115        tsb->data.w = false;
    115116        tsb->data.size = PAGESIZE_8K;
    116         tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    117         tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
    118         tsb->data.p = t->k;     /* p as privileged, k as kernel */
    119         tsb->data.v = t->p;     /* v as valid, p as present */
    120117       
    121118        write_barrier();
    122119       
    123         tsb->tag.invalid = false;       /* mark the entry as valid */
    124 #endif
     120        tsb->data.v = t->p;     /* v as valid, p as present */
    125121}
    126122
    … …  
    128124 *
    129125 * @param t     Software PTE.
    130  * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
    131126 * @param ro    If true, the mapping is copied read-only.
    132127 */
    133 void dtsb_pte_copy(pte_t *t, size_t index, bool ro)
     128void dtsb_pte_copy(pte_t *t, bool ro)
    134129{
    135 #if 0
    136130        as_t *as;
    137131        tsb_entry_t *tsb;
    138132        size_t entry;
    139        
    140         ASSERT(index <= 1);
    141133
    142134        as = t->as;
    143         entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    144         ASSERT(entry < DTSB_ENTRY_COUNT);
    145         tsb = &as->arch.dtsb[entry];
     135        entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
     136        ASSERT(entry < TSB_ENTRY_COUNT);
     137        tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
    146138
    147139        /*
    … …  
    151143         */
    152144
    153         tsb->tag.invalid = true;        /* invalidate the entry
    154                                          * (tag target has this
    155                                          * set to 0) */
     145        tsb->data.v = false;
    156146
    157147        write_barrier();
    158148
    159         tsb->tag.context = as->asid;
    160         /* the shift is bigger than PAGE_WIDTH, do not bother with index */
    161149        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
     150
    162151        tsb->data.value = 0;
    163         tsb->data.size = PAGESIZE_8K;
    164         tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    165         tsb->data.cp = t->c;
     152        tsb->data.nfo = false;
     153        tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
     154        tsb->data.ie = false;
     155        tsb->data.e = false;
     156        tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
    166157#ifdef CONFIG_VIRT_IDX_DCACHE
    167158        tsb->data.cv = t->c;
    168159#endif /* CONFIG_VIRT_IDX_DCACHE */
    169         tsb->data.p = t->k;             /* p as privileged */
     160        tsb->data.p = t->k;     /* p as privileged, k as kernel */
     161        tsb->data.x = true;
    170162        tsb->data.w = ro ? false : t->w;
    171         tsb->data.v = t->p;
     163        tsb->data.size = PAGESIZE_8K;
    172164       
    173165        write_barrier();
    174166       
    175         tsb->tag.invalid = false;       /* mark the entry as valid */
    176 #endif
     167        tsb->data.v = t->p;     /* v as valid, p as present */
    177168}
    178169
    179170/** @}
    180171 */
    181 
Note: See TracChangeset for help on using the changeset viewer.