Changeset 8c2214e in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2010-02-20T20:29:27Z (16 years ago)
Author:
Pavel Rimsky <pavel@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f516bc2
Parents:
e0cb57b
Message:

Cleanup and merge of the TSB code.

Location:
kernel/arch/sparc64/include
Files:
2 added
10 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/mm/as.h

    re0cb57b r8c2214e  
    3636#define KERN_sparc64_AS_H_
    3737
    38 #include <arch/mm/tte.h>
    39 
    40 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      1
    41 
    42 #define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0x0000000000000000
    43 #define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0xffffffffffffffff
    44 #define USER_ADDRESS_SPACE_START_ARCH           (unsigned long) 0x0000000000000000
    45 #define USER_ADDRESS_SPACE_END_ARCH             (unsigned long) 0xffffffffffffffff
    46 
    47 #define USTACK_ADDRESS_ARCH     (0xffffffffffffffffULL - (PAGE_SIZE - 1))
    48 
    49 #ifdef CONFIG_TSB
    50 
    51 /** TSB Tag Target register. */
    52 typedef union tsb_tag_target {
    53         uint64_t value;
    54         struct {
    55                 unsigned invalid : 1;   /**< Invalidated by software. */
    56                 unsigned : 2;
    57                 unsigned context : 13;  /**< Software ASID. */
    58                 unsigned : 6;
    59                 uint64_t va_tag : 42;   /**< Virtual address bits <63:22>. */
    60         } __attribute__ ((packed));
    61 } tsb_tag_target_t;
    62 
    63 /** TSB entry. */
    64 typedef struct tsb_entry {
    65         tsb_tag_target_t tag;
    66         tte_data_t data;
    67 } __attribute__ ((packed)) tsb_entry_t;
    68 
    69 typedef struct {
    70         tsb_entry_t *itsb;
    71         tsb_entry_t *dtsb;
    72 } as_arch_t;
    73 
    74 #else
    75 
    76 typedef struct {
    77 } as_arch_t;
    78 
    79 #endif /* CONFIG_TSB */
    80 
    81 #include <genarch/mm/as_ht.h>
    82 
    83 #ifdef CONFIG_TSB
    84 #include <arch/mm/tsb.h>
    85 #define as_invalidate_translation_cache(as, page, cnt) \
    86         tsb_invalidate((as), (page), (cnt))
    87 #else
    88 #define as_invalidate_translation_cache(as, page, cnt)
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/as.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/as.h>
    8942#endif
    90 
    91 extern void as_arch_init(void);
    9243
    9344#endif

  • kernel/arch/sparc64/include/mm/sun4u/tlb.h

    re0cb57b r8c2214e  
    684684
    685685extern void dump_sfsr_and_sfar(void);
     686extern void describe_dmmu_fault(void);
    686687
    687688#endif /* !def __ASM__ */

  • kernel/arch/sparc64/include/mm/sun4v/frame.h

    re0cb57b r8c2214e  
    3333 */
    3434
    35 #ifndef KERN_sparc64_SUN4V_FRAME_H_
    36 #define KERN_sparc64_SUN4V_FRAME_H_
     35#ifndef KERN_sparc64_sun4v_FRAME_H_
     36#define KERN_sparc64_sun4v_FRAME_H_
    3737
    38 /*
    39  * Page size supported by the MMU.
    40  * For 8K there is the nasty illegal virtual aliasing problem.
    41  * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
    42  */
    4338#define MMU_FRAME_WIDTH         13      /* 8K */
    4439#define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
    … …  
    5247#include <arch/types.h>
    5348
    54 union frame_address {
    55         uintptr_t address;
    56         struct {
    57 #if defined (US)
    58                 unsigned : 23;
    59                 uint64_t pfn : 28;              /**< Physical Frame Number. */
    60 #elif defined (US3)
    61                 unsigned : 21;
    62                 uint64_t pfn : 30;              /**< Physical Frame Number. */
    63 #endif
    64                 unsigned offset : 13;           /**< Offset. */
    65         } __attribute__ ((packed));
    66 };
    67 
    68 typedef union frame_address frame_address_t;
    69 
     49extern uintptr_t last_frame;
    7050extern void frame_arch_init(void);
    7151#define physmem_print()

  • kernel/arch/sparc64/include/mm/sun4v/mmu.h

    re0cb57b r8c2214e  
    4545#define ASI_SECONDARY_CONTEXT_REG       0x21    /**< secondary context register ASI. */
    4646
    47 
    48 
    49 
    50 
    51 
    52 
    53 
    54 
    55 
    56 
    57 /* I-MMU ASIs. */
    58 #define ASI_IMMU                        0x50
    59 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    60 #define ASI_IMMU_TSB_64KB_PTR_REG       0x52
    61 #define ASI_ITLB_DATA_IN_REG            0x54
    62 #define ASI_ITLB_DATA_ACCESS_REG        0x55
    63 #define ASI_ITLB_TAG_READ_REG           0x56
    64 #define ASI_IMMU_DEMAP                  0x57
    65 
    66 /* Virtual Addresses within ASI_IMMU. */
    67 #define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
    68 #define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    69 #define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
    70 #define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    71 #if defined (US3)
    72 #define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
    73 #define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
    74 #endif
    75 
    76 
    77 /* D-MMU ASIs. */
    78 #define ASI_DMMU                        0x58
    79 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    80 #define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
    81 #define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
    82 #define ASI_DTLB_DATA_IN_REG            0x5c
    83 #define ASI_DTLB_DATA_ACCESS_REG        0x5d
    84 #define ASI_DTLB_TAG_READ_REG           0x5e
    85 #define ASI_DMMU_DEMAP                  0x5f
    86 
    87 /* Virtual Addresses within ASI_DMMU. */
    88 #define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
    89 #define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
    90 #define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
    91 #define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
    92 #define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
    93 #define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
    94 #define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
    95 #define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
    96 #define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
    97 #if defined (US3)
    98 #define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
    99 #define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
    100 #define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
    101 #endif
    102 
    103 #ifndef __ASM__
    104 
    105 #include <arch/asm.h>
    106 #include <arch/barrier.h>
    107 #include <arch/types.h>
    108 
    109 #if defined(US)
    110 /** LSU Control Register. */
    111 typedef union {
    112         uint64_t value;
    113         struct {
    114                 unsigned : 23;
    115                 unsigned pm : 8;
    116                 unsigned vm : 8;
    117                 unsigned pr : 1;
    118                 unsigned pw : 1;
    119                 unsigned vr : 1;
    120                 unsigned vw : 1;
    121                 unsigned : 1;
    122                 unsigned fm : 16;       
    123                 unsigned dm : 1;        /**< D-MMU enable. */
    124                 unsigned im : 1;        /**< I-MMU enable. */
    125                 unsigned dc : 1;        /**< D-Cache enable. */
    126                 unsigned ic : 1;        /**< I-Cache enable. */
    127                
    128         } __attribute__ ((packed));
    129 } lsu_cr_reg_t;
    130 #endif /* US */
    131 
    132 #endif /* !def __ASM__ */
    133 
    134 
    135 
    136 
    137 
    138 
    139 
    140 
    141 
    142 
    143 
    144 
    145 
    146 
    147 
    148 
    14947#endif
    15048

  • kernel/arch/sparc64/include/mm/sun4v/tsb.h

    re0cb57b r8c2214e  
    7171struct pte;
    7272
    73 extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages);
     73extern void tsb_invalidate(struct as *as, uintptr_t page, uint64_t pages);
    7474extern void itsb_pte_copy(struct pte *t);
    7575extern void dtsb_pte_copy(struct pte *t, bool ro);

  • kernel/arch/sparc64/include/mm/tlb.h

    re0cb57b r8c2214e  
    3636#define KERN_sparc64_TLB_H_
    3737
     38
    3839#if defined (SUN4U)
    3940#include <arch/mm/sun4u/tlb.h>

  • kernel/arch/sparc64/include/mm/tsb.h

    re0cb57b r8c2214e  
    3636#define KERN_sparc64_TSB_H_
    3737
    38 /*
    39  * ITSB abd DTSB will claim 64K of memory, which
    40  * is a nice number considered that it is one of
    41  * the page sizes supported by hardware, which,
    42  * again, is nice because TSBs need to be locked
    43  * in TLBs - only one TLB entry will do.
    44  */
    45 #define TSB_SIZE                        2       /* when changing this, change
    46                                                  * as.c as well */
    47 #define ITSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
    48 #define DTSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
    49 
    50 #define TSB_TAG_TARGET_CONTEXT_SHIFT    48
    51 
    52 #ifndef __ASM__
    53 
    54 #include <arch/mm/tte.h>
    55 #include <arch/mm/mmu.h>
    56 #include <arch/types.h>
    57 
    58 /** TSB Base register. */
    59 typedef union tsb_base_reg {
    60         uint64_t value;
    61         struct {
    62                 uint64_t base : 51;     /**< TSB base address, bits 63:13. */
    63                 unsigned split : 1;     /**< Split vs. common TSB for 8K and 64K
    64                                          * pages. HelenOS uses only 8K pages
    65                                          * for user mappings, so we always set
    66                                          * this to 0.
    67                                          */
    68                 unsigned : 9;
    69                 unsigned size : 3;      /**< TSB size. Number of entries is
    70                                          * 512 * 2^size. */
    71         } __attribute__ ((packed));
    72 } tsb_base_reg_t;
    73 
    74 /** Read ITSB Base register.
    75  *
    76  * @return Content of the ITSB Base register.
    77  */
    78 static inline uint64_t itsb_base_read(void)
    79 {
    80         return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
    81 }
    82 
    83 /** Read DTSB Base register.
    84  *
    85  * @return Content of the DTSB Base register.
    86  */
    87 static inline uint64_t dtsb_base_read(void)
    88 {
    89         return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
    90 }
    91 
    92 /** Write ITSB Base register.
    93  *
    94  * @param v New content of the ITSB Base register.
    95  */
    96 static inline void itsb_base_write(uint64_t v)
    97 {
    98         asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
    99 }
    100 
    101 /** Write DTSB Base register.
    102  *
    103  * @param v New content of the DTSB Base register.
    104  */
    105 static inline void dtsb_base_write(uint64_t v)
    106 {
    107         asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
    108 }
    109 
    110 #if defined (US3)
    111 
    112 /** Write DTSB Primary Extension register.
    113  *
    114  * @param v New content of the DTSB Primary Extension register.
    115  */
    116 static inline void dtsb_primary_extension_write(uint64_t v)
    117 {
    118         asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
    119 }
    120 
    121 /** Write DTSB Secondary Extension register.
    122  *
    123  * @param v New content of the DTSB Secondary Extension register.
    124  */
    125 static inline void dtsb_secondary_extension_write(uint64_t v)
    126 {
    127         asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
    128 }
    129 
    130 /** Write DTSB Nucleus Extension register.
    131  *
    132  * @param v New content of the DTSB Nucleus Extension register.
    133  */
    134 static inline void dtsb_nucleus_extension_write(uint64_t v)
    135 {
    136         asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
    137 }
    138 
    139 /** Write ITSB Primary Extension register.
    140  *
    141  * @param v New content of the ITSB Primary Extension register.
    142  */
    143 static inline void itsb_primary_extension_write(uint64_t v)
    144 {
    145         asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
    146 }
    147 
    148 /** Write ITSB Nucleus Extension register.
    149  *
    150  * @param v New content of the ITSB Nucleus Extension register.
    151  */
    152 static inline void itsb_nucleus_extension_write(uint64_t v)
    153 {
    154         asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
    155 }
    156 
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/tsb.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/tsb.h>
    15742#endif
    158 
    159 /* Forward declarations. */
    160 struct as;
    161 struct pte;
    162 
    163 extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages);
    164 extern void itsb_pte_copy(struct pte *t, size_t index);
    165 extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro);
    166 
    167 #endif /* !def __ASM__ */
    16843
    16944#endif

  • kernel/arch/sparc64/include/trap/exception.h

    re0cb57b r8c2214e  
    3838
    3939#define TT_INSTRUCTION_ACCESS_EXCEPTION         0x08
     40#define TT_INSTRUCTION_ACCESS_MMU_MISS          0x09
    4041#define TT_INSTRUCTION_ACCESS_ERROR             0x0a
     42#define TT_IAE_UNAUTH_ACCESS                    0x0b
     43#define TT_IAE_NFO_PAGE                         0x0c
    4144#define TT_ILLEGAL_INSTRUCTION                  0x10
    4245#define TT_PRIVILEGED_OPCODE                    0x11
    4346#define TT_UNIMPLEMENTED_LDD                    0x12
    4447#define TT_UNIMPLEMENTED_STD                    0x13
     48#define TT_DAE_INVALID_ASI                      0x14
     49#define TT_DAE_PRIVILEGE_VIOLATION              0x15
     50#define TT_DAE_NC_PAGE                          0x16
     51#define TT_DAE_NFO_PAGE                         0x17
    4552#define TT_FP_DISABLED                          0x20
    4653#define TT_FP_EXCEPTION_IEEE_754                0x21
    … …  
    4956#define TT_DIVISION_BY_ZERO                     0x28
    5057#define TT_DATA_ACCESS_EXCEPTION                0x30
     58#define TT_DATA_ACCESS_MMU_MISS                 0x31
    5159#define TT_DATA_ACCESS_ERROR                    0x32
    5260#define TT_MEM_ADDRESS_NOT_ALIGNED              0x34

  • kernel/arch/sparc64/include/trap/sun4v/mmu.h

    re0cb57b r8c2214e  
    3636 */
    3737
    38 #ifndef KERN_sparc64_SUN4V_MMU_TRAP_H_
    39 #define KERN_sparc64_SUN4V_MMU_TRAP_H_
     38#ifndef KERN_sparc64_sun4v_MMU_TRAP_H_
     39#define KERN_sparc64_sun4v_MMU_TRAP_H_
    4040
    4141#include <arch/stack.h>
    … …  
    121121         * but this time its handler accesse memory which IS mapped.
    122122         */
    123 0:
    124 .if (\tl > 0)
    125         wrpr %g0, 1, %tl
    126 .endif
     123        .if (\tl > 0)
     124                wrpr %g0, 1, %tl
     125        .endif
    127126
    128127        /*

  • kernel/arch/sparc64/include/trap/trap_table.h

    re0cb57b r8c2214e  
    101101.macro PREEMPTIBLE_HANDLER f
    102102        sethi %hi(\f), %g1
    103         ba %xcc, preemptible_handler
     103        b preemptible_handler
    104104        or %g1, %lo(\f), %g1
    105105.endm
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