Index: kernel/arch/abs32le/include/arch/asm.h
===================================================================
--- kernel/arch/abs32le/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/abs32le/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -67,4 +67,13 @@
 }
 
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+	/*
+	 * Some ISAs have a special instruction for the body of a busy wait loop,
+	 * such as in spinlock and the like. Using it allows the CPU to optimize
+	 * its operation. For an example, see the "pause" instruction on x86.
+	 */
+}
+
 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
Index: kernel/arch/amd64/include/arch/asm.h
===================================================================
--- kernel/arch/amd64/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/amd64/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -59,5 +59,10 @@
 }
 
-#define ARCH_SPIN_HINT() asm volatile ("pause\n")
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+	asm volatile (
+	    "pause\n"
+	);
+}
 
 /** Byte from port
Index: kernel/arch/arm32/include/arch/asm.h
===================================================================
--- kernel/arch/arm32/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/arm32/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -65,7 +65,10 @@
 }
 
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
 #ifdef PROCESSOR_ARCH_armv7_a
-#define ARCH_SPIN_HINT() asm volatile ("yield")
+	asm volatile ("yield");
 #endif
+}
 
 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
Index: kernel/arch/arm64/include/arch/asm.h
===================================================================
--- kernel/arch/arm64/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/arm64/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -61,5 +61,8 @@
 }
 
-#define ARCH_SPIN_HINT() asm volatile ("yield")
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+	asm volatile ("yield");
+}
 
 /** Output byte to port.
Index: kernel/arch/ia32/include/arch/asm.h
===================================================================
--- kernel/arch/ia32/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/ia32/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -64,5 +64,10 @@
 }
 
-#define ARCH_SPIN_HINT() asm volatile ("pause\n")
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+	asm volatile (
+	    "pause\n"
+	);
+}
 
 #define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
Index: kernel/arch/ia64/include/arch/asm.h
===================================================================
--- kernel/arch/ia64/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/ia64/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -44,4 +44,8 @@
 #define IO_SPACE_BOUNDARY       ((void *) (64 * 1024))
 
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+}
+
 /** Map the I/O port address to a legacy I/O address. */
 _NO_TRACE static inline uintptr_t p2a(volatile void *p)
Index: kernel/arch/mips32/include/arch/asm.h
===================================================================
--- kernel/arch/mips32/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/mips32/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -45,4 +45,8 @@
 }
 
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+}
+
 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
Index: kernel/arch/ppc32/include/arch/asm.h
===================================================================
--- kernel/arch/ppc32/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/ppc32/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -42,4 +42,8 @@
 #include <trace.h>
 
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+}
+
 _NO_TRACE static inline uint32_t msr_read(void)
 {
Index: kernel/arch/riscv64/include/arch/asm.h
===================================================================
--- kernel/arch/riscv64/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/riscv64/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -41,4 +41,8 @@
 #include <arch/mm/asid.h>
 #include <trace.h>
+
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+}
 
 _NO_TRACE static inline ipl_t interrupts_enable(void)
Index: kernel/arch/sparc64/include/arch/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/asm.h	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/arch/sparc64/include/arch/asm.h	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -44,4 +44,8 @@
 #include <trace.h>
 
+_NO_TRACE static inline void cpu_spin_hint(void)
+{
+}
+
 _NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
Index: kernel/generic/src/synch/spinlock.c
===================================================================
--- kernel/generic/src/synch/spinlock.c	(revision 64e9cf4cb45f1c9d53cbeffc39f56cd49f6e4861)
+++ kernel/generic/src/synch/spinlock.c	(revision 8addb24acd8c8ad903505217be1dba5c2812d7a9)
@@ -49,8 +49,4 @@
 #include <cpu.h>
 
-#ifndef ARCH_SPIN_HINT
-#define ARCH_SPIN_HINT() ((void)0)
-#endif
-
 /** Initialize spinlock
  *
@@ -82,5 +78,5 @@
 
 	while (atomic_flag_test_and_set_explicit(&lock->flag, memory_order_acquire)) {
-		ARCH_SPIN_HINT();
+		cpu_spin_hint();
 
 #ifdef CONFIG_DEBUG_SPINLOCK