Changeset 8565a42 in mainline for uspace/lib/c/arch/ia64
- Timestamp:
- 2018-03-02T20:34:50Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- a1a81f69, d5e5fd1
- Parents:
- 3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)
- git-committer:
- GitHub <noreply@…> (2018-03-02 20:34:50)
- Location:
- uspace/lib/c/arch/ia64
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/lib/c/arch/ia64/_link.ld.in
r3061bc1 r8565a42 18 18 . = 0x4000 + SIZEOF_HEADERS; 19 19 #endif 20 20 21 21 /* Workaround proper alignment of the .init section */ 22 22 . = ALIGN(., 16); 23 23 24 24 .init : { 25 25 *(.init); 26 26 } :text 27 27 28 28 .text : { 29 29 *(.text .text.*); 30 30 *(.rodata .rodata.*); 31 31 } :text 32 32 33 33 #ifdef LOADER 34 34 .interp : { … … 36 36 } :interp :text 37 37 #endif 38 38 39 39 . = . + 0x4000; 40 40 41 41 .got : { 42 42 /* Tell the linker where we expect GP to point. */ … … 44 44 *(.got .got.*); 45 45 } :data 46 46 47 47 .data : { 48 48 *(.opd); … … 50 50 *(.sdata); 51 51 } :data 52 52 53 53 .tdata : { 54 54 _tdata_start = .; … … 59 59 _tbss_end = .; 60 60 } :data 61 61 62 62 _tls_alignment = ALIGNOF(.tdata); 63 63 64 64 .bss : { 65 65 *(.sbss); … … 68 68 *(.bss); 69 69 } :data 70 70 71 71 /DISCARD/ : { 72 72 *(*); -
uspace/lib/c/arch/ia64/include/libarch/atomic.h
r3061bc1 r8565a42 43 43 { 44 44 atomic_count_t v; 45 45 46 46 asm volatile ( 47 47 "fetchadd8.rel %[v] = %[count], 1\n" … … 54 54 { 55 55 atomic_count_t v; 56 56 57 57 asm volatile ( 58 58 "fetchadd8.rel %[v] = %[count], -1\n" … … 65 65 { 66 66 atomic_count_t v; 67 67 68 68 asm volatile ( 69 69 "fetchadd8.rel %[v] = %[count], 1\n" … … 71 71 [count] "+m" (val->count) 72 72 ); 73 73 74 74 return (v + 1); 75 75 } … … 78 78 { 79 79 atomic_count_t v; 80 80 81 81 asm volatile ( 82 82 "fetchadd8.rel %[v] = %[count], -1\n" … … 84 84 [count] "+m" (val->count) 85 85 ); 86 86 87 87 return (v - 1); 88 88 } … … 91 91 { 92 92 atomic_count_t v; 93 93 94 94 asm volatile ( 95 95 "fetchadd8.rel %[v] = %[count], 1\n" … … 97 97 [count] "+m" (val->count) 98 98 ); 99 99 100 100 return v; 101 101 } … … 104 104 { 105 105 atomic_count_t v; 106 106 107 107 asm volatile ( 108 108 "fetchadd8.rel %[v] = %[count], -1\n" … … 110 110 [count] "+m" (val->count) 111 111 ); 112 112 113 113 return v; 114 114 } -
uspace/lib/c/arch/ia64/src/ddi.c
r3061bc1 r8565a42 36 36 if (sysinfo_get_value("ia64_iospace.address.virtual", &addr) != 0) 37 37 addr = 0; 38 38 39 39 return addr; 40 40 } -
uspace/lib/c/arch/ia64/src/entry.S
r3061bc1 r8565a42 40 40 alloc loc0 = ar.pfs, 0, 1, 2, 0 41 41 movl gp = __gp 42 42 43 43 # Pass PCB pointer as the first argument to __main 44 44 mov out0 = r2 ;; -
uspace/lib/c/arch/ia64/src/fibril.S
r3061bc1 r8565a42 45 45 flushrs 46 46 mov loc4 = ar.bsp 47 47 48 48 /* 49 49 * Put RSE to enforced lazy mode. … … 117 117 118 118 mov loc2 = ar.unat 119 119 120 120 /* 121 121 * Save application registers … … 177 177 178 178 mov ar.unat = loc1 179 179 180 180 add r8 = r0, r0, 1 /* context_save returns 1 */ 181 181 br.ret.sptk.many b0 … … 239 239 ld8 loc5 = [loc14] /* load ar.rnat */ 240 240 ld8 loc6 = [loc15] /* load ar.lc */ 241 241 242 242 .auto 243 243 … … 274 274 mov ar.unat = loc2 ;; 275 275 mov ar.lc = loc6 276 276 277 277 /* 278 278 * Restore general registers including NaT bits … … 332 332 ldf.fill f30 = [loc48] 333 333 ldf.fill f31 = [loc49] 334 334 335 335 mov ar.unat = loc1 336 336 337 337 mov r8 = r0 /* context_restore returns 0 */ 338 338 br.ret.sptk.many b0 -
uspace/lib/c/arch/ia64/src/thread_entry.S
r3061bc1 r8565a42 38 38 39 39 movl gp = __gp 40 40 41 41 # 42 42 # r8 contains address of uarg structure. 43 43 # 44 44 45 45 mov out0 = r8 ;; 46 46 br.call.sptk.many b0 = __thread_main 47 47 48 48 # 49 49 # Not reached.
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