Changeset 8565a42 in mainline for kernel/arch/sparc64/src/mm/sun4u/tsb.c

Timestamp:

2018-03-02T20:34:50Z (8 years ago)

Author:

GitHub <noreply@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a1a81f69, d5e5fd1

Parents:

3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)

git-committer:

GitHub <noreply@…> (2018-03-02 20:34:50)

Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

File:

• kernel/arch/sparc64/src/mm/sun4u/tsb.c (modified) (6 diffs)

kernel/arch/sparc64/src/mm/sun4u/tsb.c

@@ -57 +57 @@
         size_t i;
         size_t cnt;
-        
+
         assert(as->arch.itsb);
         assert(as->arch.dtsb);
-        
+
         i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK;
 
@@ -67 +67 @@
         else
                 cnt = pages * 2;
-        
+
         for (i = 0; i < cnt; i++) {
                 as->arch.itsb[(i0 + i) & ITSB_ENTRY_MASK].tag.invalid = true;
@@ -86 +86 @@
 
         assert(index <= 1);
-        
+
         as = t->as;
         entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK;
@@ -112 +112 @@
         tte->data.p = t->k;     /* p as privileged, k as kernel */
         tte->data.v = t->p;     /* v as valid, p as present */
-        
+
         write_barrier();
-        
+
         tte->tag.invalid = false;       /* mark the entry as valid */
 }
@@ -129 +129 @@
         tsb_entry_t *tte;
         size_t entry;
-        
+
         assert(index <= 1);
 
@@ -161 +161 @@
         tte->data.w = ro ? false : t->w;
         tte->data.v = t->p;
-        
+
         write_barrier();
-        
+
         tte->tag.invalid = false;       /* mark the entry as valid */
 }