Changeset 8565a42 in mainline for kernel/arch/riscv64/src/boot

Timestamp:

2018-03-02T20:34:50Z (8 years ago)

Author:

GitHub <noreply@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a1a81f69, d5e5fd1

Parents:

3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)

git-committer:

GitHub <noreply@…> (2018-03-02 20:34:50)

Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

File:

• kernel/arch/riscv64/src/boot/boot.S (modified) (1 diff)

kernel/arch/riscv64/src/boot/boot.S

@@ -36 +36 @@
         /* Setup temporary stack */
         la sp, temp_stack
-        
+
         /* Create the first stack frame */
         addi sp, sp, -16
-        
+
         /* Call riscv64_pre_main() */
         jal riscv64_pre_main
-        
+
         /* Call main_bsp() */
         jal main_bsp
-        
+
         /* Not reached */
         csrci sstatus, SSTATUS_SIE_MASK