Changeset 8565a42 in mainline for kernel/arch/ppc32/include

Timestamp:

2018-03-02T20:34:50Z (8 years ago)

Author:

GitHub <noreply@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a1a81f69, d5e5fd1

Parents:

3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)

git-committer:

GitHub <noreply@…> (2018-03-02 20:34:50)

Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

Location:

kernel/arch/ppc32/include/arch

Files:

• asm.h (modified) (6 diffs)
• atomic.h (modified) (2 diffs)
• barrier.h (modified) (3 diffs)
• cycle.h (modified) (2 diffs)
• mm/frame.h (modified) (1 diff)
• mm/page.h (modified) (2 diffs)

kernel/arch/ppc32/include/arch/asm.h

@@ -45 +45 @@
 {
         uint32_t msr;
-        
+
         asm volatile (
                 "mfmsr %[msr]\n"
                 : [msr] "=r" (msr)
         );
-        
+
         return msr;
 }
@@ -77 +77 @@
 {
         uint32_t vsid;
-        
+
         asm volatile (
                 "mfsrin %[vsid], %[vaddr]\n"
@@ -83 +83 @@
                 : [vaddr] "r" (vaddr)
         );
-        
+
         return vsid;
 }
@@ -90 +90 @@
 {
         uint32_t sdr1;
-        
+
         asm volatile (
                 "mfsdr1 %[sdr1]\n"
                 : [sdr1] "=r" (sdr1)
         );
-        
+
         return sdr1;
 }
@@ -173 +173 @@
 {
         uintptr_t base;
-        
+
         asm volatile (
                 "and %[base], %%sp, %[mask]\n"
@@ -179 +179 @@
                 : [mask] "r" (~(STACK_SIZE - 1))
         );
-        
+
         return base;
 }

kernel/arch/ppc32/include/arch/atomic.h

@@ -41 +41 @@
 {
         atomic_count_t tmp;
-        
+
         asm volatile (
                 "1:\n"
@@ -59 +59 @@
 {
         atomic_count_t tmp;
-        
+
         asm volatile (
                 "1:\n"

kernel/arch/ppc32/include/arch/barrier.h

@@ -77 +77 @@
 {
         unsigned int i;
-        
+
         for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
                 asm volatile (
@@ -83 +83 @@
                         :: [addr] "r" (addr + i)
                 );
-        
+
         memory_barrier();
-        
+
         for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
                 asm volatile (
@@ -91 +91 @@
                         :: [addr] "r" (addr + i)
                 );
-        
+
         instruction_barrier();
 }

kernel/arch/ppc32/include/arch/cycle.h

@@ -43 +43 @@
         uint32_t upper;
         uint32_t tmp;
-        
+
         do {
                 asm volatile (
@@ -54 +54 @@
                 );
         } while (upper != tmp);
-        
+
         return ((uint64_t) upper << 32) + (uint64_t) lower;
 }

kernel/arch/ppc32/include/arch/mm/frame.h

@@ -49 +49 @@
 {
         uint32_t physmem;
-        
+
         asm volatile (
                 "mfsprg3 %[physmem]\n"
                 : [physmem] "=r" (physmem)
         );
-        
+
         return physmem;
 }

kernel/arch/ppc32/include/arch/mm/page.h

@@ -165 +165 @@
 {
         pte_t *entry = &pt[i];
-        
+
         return (((!entry->page_cache_disable) << PAGE_CACHEABLE_SHIFT) |
             ((!entry->present) << PAGE_PRESENT_SHIFT) |
@@ -178 +178 @@
 {
         pte_t *entry = &pt[i];
-        
+
         entry->page_cache_disable = !(flags & PAGE_CACHEABLE);
         entry->present = !(flags & PAGE_NOT_PRESENT);