Changeset 8565a42 in mainline for kernel/arch/ia32/src/drivers/i8254.c


Ignore:
Timestamp:
2018-03-02T20:34:50Z (8 years ago)
Author:
GitHub <noreply@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a1a81f69, d5e5fd1
Parents:
3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
git-author:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)
git-committer:
GitHub <noreply@…> (2018-03-02 20:34:50)
Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/src/drivers/i8254.c

    r3061bc1 r8565a42  
    8989        i8254_irq.handler = i8254_irq_handler;
    9090        irq_register(&i8254_irq);
    91        
     91
    9292        i8254_normal_operation();
    9393}
     
    111111        pio_write_8(CLK_PORT1, 0xff);
    112112        pio_write_8(CLK_PORT1, 0xff);
    113        
     113
    114114        uint8_t not_ok;
    115115        uint32_t t1;
    116116        uint32_t t2;
    117        
     117
    118118        do {
    119119                /* will read both status and count */
     
    123123                t1 |= pio_read_8(CLK_PORT1) << 8;
    124124        } while (not_ok);
    125        
     125
    126126        asm_delay_loop(LOOPS);
    127        
     127
    128128        pio_write_8(CLK_PORT4, 0xd2);
    129129        t2 = pio_read_8(CLK_PORT1);
    130130        t2 |= pio_read_8(CLK_PORT1) << 8;
    131        
     131
    132132        /*
    133133         * We want to determine the overhead of the calibrating mechanism.
     
    136136        uint32_t o1 = pio_read_8(CLK_PORT1);
    137137        o1 |= pio_read_8(CLK_PORT1) << 8;
    138        
     138
    139139        asm_fake_loop(LOOPS);
    140        
     140
    141141        pio_write_8(CLK_PORT4, 0xd2);
    142142        uint32_t o2 = pio_read_8(CLK_PORT1);
    143143        o2 |= pio_read_8(CLK_PORT1) << 8;
    144        
     144
    145145        CPU->delay_loop_const =
    146146            ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) +
    147147            (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0);
    148        
     148
    149149        uint64_t clk1 = get_cycle();
    150150        delay(1 << SHIFT);
    151151        uint64_t clk2 = get_cycle();
    152        
     152
    153153        CPU->frequency_mhz = (clk2 - clk1) >> SHIFT;
    154        
     154
    155155        return;
    156156}
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