Index: kernel/arch/abs32le/include/istate.h
===================================================================
--- kernel/arch/abs32le/include/istate.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/abs32le/include/istate.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -37,13 +37,18 @@
 
 #ifdef KERNEL
+
 #include <typedefs.h>
 #include <verify.h>
 #include <trace.h>
-#else
+
+#else /* KERNEL */
+
 #include <sys/types.h>
+
 #define NO_TRACE
 #define REQUIRES_EXTENT_MUTABLE(arg)
 #define WRITES(arg)
-#endif
+
+#endif /* KERNEL */
 
 /*
@@ -63,5 +68,5 @@
 	   context originated from user space. */
 	
-	return !(istate->ip & 0x80000000);
+	return !(istate->ip & UINT32_C(0x80000000));
 }
 
Index: kernel/arch/abs32le/include/mm/as.h
===================================================================
--- kernel/arch/abs32le/include/mm/as.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/abs32le/include/mm/as.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -38,8 +38,8 @@
 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
 
-#define KERNEL_ADDRESS_SPACE_START_ARCH  ((unsigned long) 0x80000000)
-#define KERNEL_ADDRESS_SPACE_END_ARCH    ((unsigned long) 0xffffffff)
-#define USER_ADDRESS_SPACE_START_ARCH    ((unsigned long) 0x00000000)
-#define USER_ADDRESS_SPACE_END_ARCH      ((unsigned long) 0x7fffffff)
+#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
+#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
+#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
+#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
 
 #define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
Index: kernel/arch/abs32le/include/mm/page.h
===================================================================
--- kernel/arch/abs32le/include/mm/page.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/abs32le/include/mm/page.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -44,6 +44,6 @@
 #ifdef KERNEL
 
-#define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
-#define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
+#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
+#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
 
 /*
@@ -65,8 +65,8 @@
 
 /* Macros calculating indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
+#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
 #define PTL1_INDEX_ARCH(vaddr)  0
 #define PTL2_INDEX_ARCH(vaddr)  0
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
 
 /* Get PTE address accessors for each level. */
Index: kernel/arch/abs32le/include/types.h
===================================================================
--- kernel/arch/abs32le/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/abs32le/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -53,24 +53,9 @@
 } fncptr_t;
 
-#define PRIp  "x"  /**< Format for uintptr_t. */
-#define PRIs  "u"  /**< Format for size_t. */
-
-#define PRId8   "d"    /**< Format for int8_t. */
-#define PRId16  "d"    /**< Format for int16_t. */
-#define PRId32  "d"    /**< Format for int32_t. */
-#define PRId64  "lld"  /**< Format for int64_t. */
-#define PRIdn   "d"    /**< Format for native_t. */
-
-#define PRIu8   "u"    /**< Format for uint8_t. */
-#define PRIu16  "u"    /**< Format for uint16_t. */
-#define PRIu32  "u"    /**< Format for uint32_t. */
-#define PRIu64  "llu"  /**< Format for uint64_t. */
-#define PRIun   "u"    /**< Format for unative_t. */
-
-#define PRIx8   "x"    /**< Format for hexadecimal (u)int8_t. */
-#define PRIx16  "x"    /**< Format for hexadecimal (u)int16_t. */
-#define PRIx32  "x"    /**< Format for hexadecimal (u)uint32_t. */
-#define PRIx64  "llx"  /**< Format for hexadecimal (u)int64_t. */
-#define PRIxn   "x"    /**< Format for hexadecimal (u)native_t. */
+#define PRIp   PRIx32  /**< Format for uintptr_t. */
+#define PRIs   PRIu32  /**< Format for size_t. */
+#define PRIdn  PRId32  /**< Format for native_t. */
+#define PRIun  PRIu32  /**< Format for unative_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/amd64/include/context.h
===================================================================
--- kernel/arch/amd64/include/context.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/context.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amd64	
+/** @addtogroup amd64
  * @{
  */
@@ -44,5 +44,5 @@
  * panic sooner or later
  */
-#define SP_DELTA     16
+#define SP_DELTA  16
 
 #define context_set(c, _pc, stack, size) \
Index: kernel/arch/amd64/include/context_offset.h
===================================================================
--- kernel/arch/amd64/include/context_offset.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/context_offset.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -30,22 +30,22 @@
 #define KERN_amd64_CONTEXT_OFFSET_H_
 
-#define OFFSET_SP  0x0
-#define OFFSET_PC  0x8
-#define OFFSET_RBX 0x10
-#define OFFSET_RBP 0x18
-#define OFFSET_R12 0x20
-#define OFFSET_R13 0x28
-#define OFFSET_R14 0x30
-#define OFFSET_R15 0x38
+#define OFFSET_SP   0x00
+#define OFFSET_PC   0x08
+#define OFFSET_RBX  0x10
+#define OFFSET_RBP  0x18
+#define OFFSET_R12  0x20
+#define OFFSET_R13  0x28
+#define OFFSET_R14  0x30
+#define OFFSET_R15  0x38
 
 #ifdef KERNEL
-# define OFFSET_IPL 0x40
+	#define OFFSET_IPL  0x40
 #else
-# define OFFSET_TLS 0x40
+	#define OFFSET_TLS  0x40
 #endif
 
 #ifdef __ASM__
 
-# ctx: address of the structure with saved context 
+# ctx: address of the structure with saved context
 # pc: return address
 .macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
@@ -61,5 +61,5 @@
 .endm
 
-# ctx: address of the structure with saved context 
+# ctx: address of the structure with saved context
 .macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
 	movq OFFSET_R15(\ctx), %r15
@@ -68,5 +68,5 @@
 	movq OFFSET_R12(\ctx), %r12
 	movq OFFSET_RBP(\ctx), %rbp
-	movq OFFSET_RBX(\ctx), %rbx	
+	movq OFFSET_RBX(\ctx), %rbx
 	
 	movq OFFSET_SP(\ctx), %rsp   # ctx->sp -> %rsp
Index: kernel/arch/amd64/include/cpu.h
===================================================================
--- kernel/arch/amd64/include/cpu.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/cpu.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -36,15 +36,15 @@
 #define KERN_amd64_CPU_H_
 
-#define RFLAGS_CF	(1 << 0)
-#define RFLAGS_PF	(1 << 2)
-#define RFLAGS_AF	(1 << 4)
-#define RFLAGS_ZF	(1 << 6)
-#define RFLAGS_SF	(1 << 7)
-#define RFLAGS_TF	(1 << 8)
-#define RFLAGS_IF	(1 << 9)
-#define RFLAGS_DF	(1 << 10)
-#define RFLAGS_OF	(1 << 11)
-#define RFLAGS_NT	(1 << 14)
-#define RFLAGS_RF	(1 << 16)
+#define RFLAGS_CF  (1 << 0)
+#define RFLAGS_PF  (1 << 2)
+#define RFLAGS_AF  (1 << 4)
+#define RFLAGS_ZF  (1 << 6)
+#define RFLAGS_SF  (1 << 7)
+#define RFLAGS_TF  (1 << 8)
+#define RFLAGS_IF  (1 << 9)
+#define RFLAGS_DF  (1 << 10)
+#define RFLAGS_OF  (1 << 11)
+#define RFLAGS_NT  (1 << 14)
+#define RFLAGS_RF  (1 << 16)
 
 #define EFER_MSR_NUM    0xc0000080
Index: kernel/arch/amd64/include/debugger.h
===================================================================
--- kernel/arch/amd64/include/debugger.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/debugger.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -41,9 +41,9 @@
 
 /* Flags that are passed to breakpoint_add function */
-#define BKPOINT_INSTR       0x1
-#define BKPOINT_WRITE       0x2
-#define BKPOINT_READ_WRITE  0x4
+#define BKPOINT_INSTR       0x1U
+#define BKPOINT_WRITE       0x2U
+#define BKPOINT_READ_WRITE  0x4U
 
-#define BKPOINT_CHECK_ZERO  0x8
+#define BKPOINT_CHECK_ZERO  0x8U
 
 
Index: kernel/arch/amd64/include/istate.h
===================================================================
--- kernel/arch/amd64/include/istate.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/istate.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -37,10 +37,15 @@
 
 #ifdef KERNEL
+
 #include <typedefs.h>
 #include <trace.h>
-#else
+
+#else /* KERNEL */
+
 #include <sys/types.h>
+
 #define NO_TRACE
-#endif
+
+#endif /* KERNEL */
 
 /** This is passed to interrupt handlers */
@@ -61,13 +66,13 @@
 	uint64_t r14;
 	uint64_t r15;
-	uint64_t alignment;	/* align rbp_frame on multiple of 16 */
-	uint64_t rbp_frame;	/* imitation of frame pointer linkage */
-	uint64_t rip_frame;	/* imitation of return address linkage */
-	uint64_t error_word;	/* real or fake error word */
+	uint64_t alignment;   /* align rbp_frame on multiple of 16 */
+	uint64_t rbp_frame;   /* imitation of frame pointer linkage */
+	uint64_t rip_frame;   /* imitation of return address linkage */
+	uint64_t error_word;  /* real or fake error word */
 	uint64_t rip;
 	uint64_t cs;
 	uint64_t rflags;
-	uint64_t rsp;		/* only if istate_t is from uspace */
-	uint64_t ss;		/* only if istate_t is from uspace */
+	uint64_t rsp;         /* only if istate_t is from uspace */
+	uint64_t ss;          /* only if istate_t is from uspace */
 } istate_t;
 
@@ -75,5 +80,5 @@
 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
-	return !(istate->rip & 0x8000000000000000);
+	return !(istate->rip & UINT64_C(0x8000000000000000));
 }
 
Index: kernel/arch/amd64/include/mm/as.h
===================================================================
--- kernel/arch/amd64/include/mm/as.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/mm/as.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -36,14 +36,14 @@
 #define KERN_amd64_AS_H_
 
-#define ADDRESS_SPACE_HOLE_START	0x0000800000000000ULL
-#define ADDRESS_SPACE_HOLE_END		0xffff7fffffffffffULL
+#define ADDRESS_SPACE_HOLE_START  UINT64_C(0x0000800000000000)
+#define ADDRESS_SPACE_HOLE_END    UINT64_C(0xffff7fffffffffff)
 
 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
 
-#define KERNEL_ADDRESS_SPACE_START_ARCH	0xffff800000000000ULL
-#define KERNEL_ADDRESS_SPACE_END_ARCH	0xffffffffffffffffULL
+#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT64_C(0xffff800000000000)
+#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT64_C(0xffffffffffffffff)
 
-#define USER_ADDRESS_SPACE_START_ARCH	0x0000000000000000ULL
-#define USER_ADDRESS_SPACE_END_ARCH	0x00007fffffffffffULL
+#define USER_ADDRESS_SPACE_START_ARCH  UINT64_C(0x0000000000000000)
+#define USER_ADDRESS_SPACE_END_ARCH    UINT64_C(0x00007fffffffffff)
 
 #define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
Index: kernel/arch/amd64/include/mm/page.h
===================================================================
--- kernel/arch/amd64/include/mm/page.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/mm/page.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -55,6 +55,6 @@
 #ifndef __ASM__
 
-#define KA2PA(x)  (((uintptr_t) (x)) - 0xffff800000000000)
-#define PA2KA(x)  (((uintptr_t) (x)) + 0xffff800000000000)
+#define KA2PA(x)  (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
+#define PA2KA(x)  (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
 
 #else /* __ASM__ */
@@ -78,8 +78,8 @@
 
 /* Macros calculating indices into page tables in each level. */
-#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ff)
-#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ff)
-#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ff)
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ff)
+#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ffU)
+#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ffU)
+#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ffU)
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ffU)
 
 /* Get PTE address accessors for each level. */
@@ -205,5 +205,5 @@
 	pte_t *p = &pt[i];
 	
-	p->addr_12_31 = (a >> 12) & 0xfffff;
+	p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
 	p->addr_32_51 = a >> 32;
 }
Index: kernel/arch/amd64/include/pm.h
===================================================================
--- kernel/arch/amd64/include/pm.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/pm.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -75,7 +75,7 @@
 #define AR_WRITABLE   (1 << 1)
 #define AR_READABLE   (1 << 1)
-#define AR_TSS        (0x09)
-#define AR_INTERRUPT  (0x0e)
-#define AR_TRAP       (0x0f)
+#define AR_TSS        (0x09U)
+#define AR_INTERRUPT  (0x0eU)
+#define AR_TRAP       (0x0fU)
 
 #define DPL_KERNEL  (PL_KERNEL << 5)
Index: kernel/arch/amd64/include/types.h
===================================================================
--- kernel/arch/amd64/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -50,26 +50,9 @@
 } fncptr_t;
 
-/* Formats for uintptr_t, size_t */
-#define PRIp  "llx"
-#define PRIs  "llu"
-
-/* Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
-#define PRId8   "d"
-#define PRId16  "d"
-#define PRId32  "d"
-#define PRId64  "lld"
-#define PRIdn   "lld"
-
-#define PRIu8   "u"
-#define PRIu16  "u"
-#define PRIu32  "u"
-#define PRIu64  "llu"
-#define PRIun   "llu"
-
-#define PRIx8   "x"
-#define PRIx16  "x"
-#define PRIx32  "x"
-#define PRIx64  "llx"
-#define PRIxn   "llx"
+#define PRIp   PRIx64  /**< Format for uintptr_t. */
+#define PRIs   PRIu64  /**< Format for size_t. */
+#define PRIdn  PRId64  /**< Format for native_t. */
+#define PRIun  PRIu64  /**< Format for unative_t. */
+#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/amd64/src/boot/memmap.c
===================================================================
--- kernel/arch/amd64/src/boot/memmap.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/src/boot/memmap.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -35,5 +35,5 @@
 #include <arch/boot/memmap.h>
 
-uint8_t e820counter = 0xff;
+uint8_t e820counter = 0xffU;
 e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
 
Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -47,12 +47,11 @@
  * Contains only non-MP-Specification specific SMP code.
  */
-#define AMD_CPUID_EBX  0x68747541
-#define AMD_CPUID_ECX  0x444d4163
-#define AMD_CPUID_EDX  0x69746e65
+#define AMD_CPUID_EBX  UINT32_C(0x68747541)
+#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
+#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
 
-#define INTEL_CPUID_EBX  0x756e6547
-#define INTEL_CPUID_ECX  0x6c65746e
-#define INTEL_CPUID_EDX  0x49656e69
-
+#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
+#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
+#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
 
 enum vendor {
Index: kernel/arch/amd64/src/debugger.c
===================================================================
--- kernel/arch/amd64/src/debugger.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/src/debugger.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -126,5 +126,5 @@
 	/* Disable breakpoint in DR7 */
 	unative_t dr7 = read_dr7();
-	dr7 &= ~(0x2 << (curidx * 2));
+	dr7 &= ~(0x02U << (curidx * 2));
 	
 	/* Setup DR register */
@@ -147,24 +147,24 @@
 		
 		/* Set type to requested breakpoint & length*/
-		dr7 &= ~(0x3 << (16 + 4 * curidx));
-		dr7 &= ~(0x3 << (18 + 4 * curidx));
+		dr7 &= ~(0x03U << (16 + 4 * curidx));
+		dr7 &= ~(0x03U << (18 + 4 * curidx));
 		
 		if (!(flags & BKPOINT_INSTR)) {
 #ifdef __32_BITS__
-			dr7 |= ((unative_t) 0x3) << (18 + 4 * curidx);
+			dr7 |= ((unative_t) 0x03U) << (18 + 4 * curidx);
 #endif
 			
 #ifdef __64_BITS__
-			dr7 |= ((unative_t) 0x2) << (18 + 4 * curidx);
+			dr7 |= ((unative_t) 0x02U) << (18 + 4 * curidx);
 #endif
 			
 			if ((flags & BKPOINT_WRITE))
-				dr7 |= ((unative_t) 0x1) << (16 + 4 * curidx);
+				dr7 |= ((unative_t) 0x01U) << (16 + 4 * curidx);
 			else if ((flags & BKPOINT_READ_WRITE))
-				dr7 |= ((unative_t) 0x3) << (16 + 4 * curidx);
+				dr7 |= ((unative_t) 0x03U) << (16 + 4 * curidx);
 		}
 		
 		/* Enable global breakpoint */
-		dr7 |= 0x2 << (curidx * 2);
+		dr7 |= 0x02U << (curidx * 2);
 		
 		write_dr7(dr7);
Index: kernel/arch/amd64/src/pm.c
===================================================================
--- kernel/arch/amd64/src/pm.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/amd64/src/pm.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -28,5 +28,5 @@
  */
 
-/** @addtogroup amd64	
+/** @addtogroup amd64
  * @{
  */
@@ -52,57 +52,57 @@
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 	/* KTEXT descriptor */
-	{ .limit_0_15  = 0xffff, 
-	  .base_0_15   = 0, 
-	  .base_16_23  = 0, 
-	  .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
-	  .limit_16_19 = 0xf, 
-	  .available   = 0, 
-	  .longmode    = 1, 
+	{ .limit_0_15  = 0xffffU,
+	  .base_0_15   = 0,
+	  .base_16_23  = 0,
+	  .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
+	  .limit_16_19 = 0x0fU,
+	  .available   = 0,
+	  .longmode    = 1,
 	  .special     = 0,
-	  .granularity = 1, 
+	  .granularity = 1,
 	  .base_24_31  = 0 },
 	/* KDATA descriptor */
-	{ .limit_0_15  = 0xffff, 
-	  .base_0_15   = 0, 
-	  .base_16_23  = 0, 
-	  .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 
-	  .limit_16_19 = 0xf, 
-	  .available   = 0, 
-	  .longmode    = 0, 
-	  .special     = 0, 
-	  .granularity = 1, 
+	{ .limit_0_15  = 0xffffU,
+	  .base_0_15   = 0,
+	  .base_16_23  = 0,
+	  .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
+	  .limit_16_19 = 0x0fU,
+	  .available   = 0,
+	  .longmode    = 0,
+	  .special     = 0,
+	  .granularity = 1,
 	  .base_24_31  = 0 },
 	/* UDATA descriptor */
-	{ .limit_0_15  = 0xffff, 
-	  .base_0_15   = 0, 
-	  .base_16_23  = 0, 
-	  .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 
-	  .limit_16_19 = 0xf, 
-	  .available   = 0, 
-	  .longmode    = 0, 
-	  .special     = 1, 
-	  .granularity = 1, 
+	{ .limit_0_15  = 0xffffU,
+	  .base_0_15   = 0,
+	  .base_16_23  = 0,
+	  .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
+	  .limit_16_19 = 0x0fU,
+	  .available   = 0,
+	  .longmode    = 0,
+	  .special     = 1,
+	  .granularity = 1,
 	  .base_24_31  = 0 },
 	/* UTEXT descriptor */
-	{ .limit_0_15  = 0xffff, 
-	  .base_0_15   = 0, 
-	  .base_16_23  = 0, 
-	  .access      = AR_PRESENT | AR_CODE | DPL_USER, 
-	  .limit_16_19 = 0xf, 
-	  .available   = 0, 
-	  .longmode    = 1, 
-	  .special     = 0, 
-	  .granularity = 1, 
+	{ .limit_0_15  = 0xffffU,
+	  .base_0_15   = 0,
+	  .base_16_23  = 0,
+	  .access      = AR_PRESENT | AR_CODE | DPL_USER,
+	  .limit_16_19 = 0x0fU,
+	  .available   = 0,
+	  .longmode    = 1,
+	  .special     = 0,
+	  .granularity = 1,
 	  .base_24_31  = 0 },
 	/* KTEXT 32-bit protected, for protected mode before long mode */
-	{ .limit_0_15  = 0xffff, 
-	  .base_0_15   = 0, 
-	  .base_16_23  = 0, 
-	  .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
-	  .limit_16_19 = 0xf, 
-	  .available   = 0, 
-	  .longmode    = 0, 
+	{ .limit_0_15  = 0xffffU,
+	  .base_0_15   = 0,
+	  .base_16_23  = 0,
+	  .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
+	  .limit_16_19 = 0x0fU,
+	  .available   = 0,
+	  .longmode    = 0,
 	  .special     = 1,
-	  .granularity = 1, 
+	  .granularity = 1,
 	  .base_24_31  = 0 },
 	/* TSS descriptor - set up will be completed later,
@@ -111,7 +111,8 @@
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 	/* VESA Init descriptor */
-#ifdef CONFIG_FB	
-	{ 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
-	  0xf, 0, 0, 0, 0, 0
+#ifdef CONFIG_FB
+	{
+		0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
+		    0xf, 0, 0, 0, 0, 0
 	}
 #endif
@@ -129,8 +130,8 @@
 {
 	tss_descriptor_t *td = (tss_descriptor_t *) d;
-
-	td->base_0_15 = base & 0xffff;
-	td->base_16_23 = ((base) >> 16) & 0xff;
-	td->base_24_31 = ((base) >> 24) & 0xff;
+	
+	td->base_0_15 = base & 0xffffU;
+	td->base_16_23 = ((base) >> 16) & 0xffU;
+	td->base_24_31 = ((base) >> 24) & 0xffU;
 	td->base_32_63 = ((base) >> 32);
 }
@@ -140,6 +141,6 @@
 	tss_descriptor_t *td = (tss_descriptor_t *) d;
 	
-	td->limit_0_15 = limit & 0xffff;
-	td->limit_16_19 = (limit >> 16) & 0xf;
+	td->limit_0_15 = limit & 0xffffU;
+	td->limit_16_19 = (limit >> 16) & 0x0fU;
 }
 
@@ -149,6 +150,6 @@
 	 * Offset is a linear address.
 	 */
-	d->offset_0_15 = offset & 0xffff;
-	d->offset_16_31 = offset >> 16 & 0xffff;
+	d->offset_0_15 = offset & 0xffffU;
+	d->offset_16_31 = (offset >> 16) & 0xffffU;
 	d->offset_32_63 = offset >> 32;
 }
@@ -165,16 +166,16 @@
 {
 	idescriptor_t *d;
-	int i;
-
+	unsigned int i;
+	
 	for (i = 0; i < IDT_ITEMS; i++) {
 		d = &idt[i];
-
+		
 		d->unused = 0;
 		d->selector = GDT_SELECTOR(KTEXT_DES);
-
+		
 		d->present = 1;
-		d->type = AR_INTERRUPT;	/* masking interrupt */
+		d->type = AR_INTERRUPT;  /* masking interrupt */
 	}
-
+	
 	d = &idt[0];
 	idt_setoffset(d++, (uintptr_t) &int_0);
Index: kernel/arch/arm32/include/types.h
===================================================================
--- kernel/arch/arm32/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/arm32/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -57,24 +57,9 @@
 } fncptr_t;
 
-#define PRIp "x"  /**< Format for uintptr_t. */
-#define PRIs "u"  /**< Format for size_t. */
-
-#define PRId8 "d"     /**< Format for int8_t. */
-#define PRId16 "d"    /**< Format for int16_t. */
-#define PRId32 "d"    /**< Format for int32_t. */
-#define PRId64 "lld"  /**< Format for int64_t. */
-#define PRIdn "d"     /**< Format for native_t. */
-
-#define PRIu8 "u"     /**< Format for uint8_t. */
-#define PRIu16 "u"    /**< Format for uint16_t. */
-#define PRIu32 "u"    /**< Format for uint32_t. */
-#define PRIu64 "llu"  /**< Format for uint64_t. */
-#define PRIun "u"     /**< Format for unative_t. */
-
-#define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
-#define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
-#define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
-#define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
-#define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
+#define PRIp   PRIx32  /**< Format for uintptr_t. */
+#define PRIs   PRIu32  /**< Format for size_t. */
+#define PRIdn  PRId32  /**< Format for native_t. */
+#define PRIun  PRIu32  /**< Format for unative_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/ia32/include/boot/boot.h
===================================================================
--- kernel/arch/ia32/include/boot/boot.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/boot/boot.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -38,5 +38,5 @@
 #define BOOT_OFFSET      0x108000
 #define AP_BOOT_OFFSET   0x8000
-#define BOOT_STACK_SIZE  0x400
+#define BOOT_STACK_SIZE  0x0400
 
 #define MULTIBOOT_HEADER_MAGIC  0x1BADB002
Index: kernel/arch/ia32/include/boot/memmap.h
===================================================================
--- kernel/arch/ia32/include/boot/memmap.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/boot/memmap.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -70,5 +70,5 @@
 
 extern e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
-extern uint8_t e820counter; 
+extern uint8_t e820counter;
 
 #endif
Index: kernel/arch/ia32/include/context.h
===================================================================
--- kernel/arch/ia32/include/context.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/context.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia32	
+/** @addtogroup ia32
  * @{
  */
@@ -40,5 +40,5 @@
 #include <typedefs.h>
 
-#define STACK_ITEM_SIZE	4
+#define STACK_ITEM_SIZE  4
 
 /*
@@ -48,5 +48,5 @@
  * One item is put onto stack to support get_stack_base().
  */
-#define SP_DELTA	(8 + STACK_ITEM_SIZE)
+#define SP_DELTA  (8 + STACK_ITEM_SIZE)
 
 #define context_set(c, _pc, stack, size) \
Index: kernel/arch/ia32/include/context_offset.h
===================================================================
--- kernel/arch/ia32/include/context_offset.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/context_offset.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia32	
+/** @addtogroup ia32
  * @{
  */
@@ -36,33 +36,32 @@
 #define KERN_ia32_CONTEXT_OFFSET_H_
 
-#define OFFSET_SP  0x0
-#define OFFSET_PC  0x4
-#define OFFSET_EBX 0x8
-#define OFFSET_ESI 0xC
-#define OFFSET_EDI 0x10
-#define OFFSET_EBP 0x14
+#define OFFSET_SP   0x00
+#define OFFSET_PC   0x04
+#define OFFSET_EBX  0x08
+#define OFFSET_ESI  0x0C
+#define OFFSET_EDI  0x10
+#define OFFSET_EBP  0x14
 
-#ifdef KERNEL 
-# define OFFSET_IPL 0x18
+#ifdef KERNEL
+	#define OFFSET_IPL  0x18
 #else
-# define OFFSET_TLS 0x18
+	#define OFFSET_TLS  0x18
 #endif
 
+#ifdef __ASM__
 
-#ifdef __ASM__ 
-
-# ctx: address of the structure with saved context 
+# ctx: address of the structure with saved context
 # pc: return address
 
 .macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
-	movl %esp,OFFSET_SP(\ctx)	# %esp -> ctx->sp	
+	movl %esp,OFFSET_SP(\ctx)	# %esp -> ctx->sp
 	movl \pc,OFFSET_PC(\ctx)	# %eip -> ctx->pc
-	movl %ebx,OFFSET_EBX(\ctx)	# %ebx -> ctx->ebx	
-	movl %esi,OFFSET_ESI(\ctx)	# %esi -> ctx->esi	
-	movl %edi,OFFSET_EDI(\ctx)	# %edi -> ctx->edi	
-	movl %ebp,OFFSET_EBP(\ctx)	# %ebp -> ctx->ebp	
+	movl %ebx,OFFSET_EBX(\ctx)	# %ebx -> ctx->ebx
+	movl %esi,OFFSET_ESI(\ctx)	# %esi -> ctx->esi
+	movl %edi,OFFSET_EDI(\ctx)	# %edi -> ctx->edi
+	movl %ebp,OFFSET_EBP(\ctx)	# %ebp -> ctx->ebp
 .endm
 
-# ctx: address of the structure with saved context 
+# ctx: address of the structure with saved context
 
 .macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
@@ -75,5 +74,5 @@
 .endm
 
-#endif /* __ASM__ */ 
+#endif /* __ASM__ */
 
 #endif
@@ -81,3 +80,2 @@
 /** @}
  */
-
Index: kernel/arch/ia32/include/cpu.h
===================================================================
--- kernel/arch/ia32/include/cpu.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/cpu.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -44,7 +44,7 @@
 
 /* Support for SYSENTER and SYSEXIT */
-#define IA32_MSR_SYSENTER_CS	0x174
-#define IA32_MSR_SYSENTER_ESP	0x175
-#define IA32_MSR_SYSENTER_EIP	0x176
+#define IA32_MSR_SYSENTER_CS   0x174U
+#define IA32_MSR_SYSENTER_ESP  0x175U
+#define IA32_MSR_SYSENTER_EIP  0x176U
 
 #ifndef __ASM__
Index: kernel/arch/ia32/include/drivers/i8259.h
===================================================================
--- kernel/arch/ia32/include/drivers/i8259.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/drivers/i8259.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -39,8 +39,8 @@
 #include <arch/interrupt.h>
 
-#define PIC_PIC0PORT1  ((ioport8_t *) 0x20)
-#define PIC_PIC0PORT2  ((ioport8_t *) 0x21)
-#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0)
-#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1)
+#define PIC_PIC0PORT1  ((ioport8_t *) 0x20U)
+#define PIC_PIC0PORT2  ((ioport8_t *) 0x21U)
+#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0U)
+#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1U)
 
 #define PIC_NEEDICW4  (1 << 0)
Index: kernel/arch/ia32/include/istate.h
===================================================================
--- kernel/arch/ia32/include/istate.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/istate.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -37,10 +37,15 @@
 
 #ifdef KERNEL
+
 #include <typedefs.h>
 #include <trace.h>
-#else
+
+#else /* KERNEL */
+
 #include <sys/types.h>
+
 #define NO_TRACE
-#endif
+
+#endif /* KERNEL */
 
 typedef struct istate {
@@ -77,5 +82,5 @@
 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
-	return !(istate->eip & 0x80000000);
+	return !(istate->eip & UINT32_C(0x80000000));
 }
 
Index: kernel/arch/ia32/include/mm/as.h
===================================================================
--- kernel/arch/ia32/include/mm/as.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/mm/as.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -36,12 +36,12 @@
 #define KERN_ia32_AS_H_
 
-#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH	0
+#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
 
-#define KERNEL_ADDRESS_SPACE_START_ARCH		((unsigned long) 0x80000000)
-#define KERNEL_ADDRESS_SPACE_END_ARCH		((unsigned long) 0xffffffff)
-#define USER_ADDRESS_SPACE_START_ARCH		((unsigned long) 0x00000000)
-#define USER_ADDRESS_SPACE_END_ARCH		((unsigned long) 0x7fffffff)
+#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
+#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
+#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
+#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
 
-#define USTACK_ADDRESS_ARCH	(USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
+#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
 
 typedef struct {
@@ -50,7 +50,7 @@
 #include <genarch/mm/as_pt.h>
 
-#define as_constructor_arch(as, flags)		(as != as)
-#define as_destructor_arch(as)			(as != as)
-#define as_create_arch(as, flags)		(as != as)
+#define as_constructor_arch(as, flags)  (as != as)
+#define as_destructor_arch(as)          (as != as)
+#define as_create_arch(as, flags)       (as != as)
 #define as_install_arch(as)
 #define as_deinstall_arch(as)
Index: kernel/arch/ia32/include/mm/page.h
===================================================================
--- kernel/arch/ia32/include/mm/page.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/mm/page.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -39,16 +39,20 @@
 #include <trace.h>
 
-#define PAGE_WIDTH	FRAME_WIDTH
-#define PAGE_SIZE	FRAME_SIZE
+#define PAGE_WIDTH  FRAME_WIDTH
+#define PAGE_SIZE   FRAME_SIZE
 
 #ifdef KERNEL
 
 #ifndef __ASM__
-#	define KA2PA(x)	(((uintptr_t) (x)) - 0x80000000)
-#	define PA2KA(x)	(((uintptr_t) (x)) + 0x80000000)
-#else
-#	define KA2PA(x)	((x) - 0x80000000)
-#	define PA2KA(x)	((x) + 0x80000000)
-#endif
+
+#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
+#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
+
+#else /* __ASM__ */
+
+#define KA2PA(x)  ((x) - 0x80000000)
+#define PA2KA(x)  ((x) + 0x80000000)
+
+#endif /* __ASM__ */
 
 /*
@@ -58,20 +62,20 @@
 
 /* Number of entries in each level. */
-#define PTL0_ENTRIES_ARCH	1024
-#define PTL1_ENTRIES_ARCH	0
-#define PTL2_ENTRIES_ARCH	0
-#define PTL3_ENTRIES_ARCH	1024
+#define PTL0_ENTRIES_ARCH  1024
+#define PTL1_ENTRIES_ARCH  0
+#define PTL2_ENTRIES_ARCH  0
+#define PTL3_ENTRIES_ARCH  1024
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH		ONE_FRAME
-#define PTL1_SIZE_ARCH		0
-#define PTL2_SIZE_ARCH		0
-#define PTL3_SIZE_ARCH		ONE_FRAME
+#define PTL0_SIZE_ARCH  ONE_FRAME
+#define PTL1_SIZE_ARCH  0
+#define PTL2_SIZE_ARCH  0
+#define PTL3_SIZE_ARCH  ONE_FRAME
 
 /* Macros calculating indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)	(((vaddr) >> 22) & 0x3ff)
-#define PTL1_INDEX_ARCH(vaddr)	0
-#define PTL2_INDEX_ARCH(vaddr)	0
-#define PTL3_INDEX_ARCH(vaddr)	(((vaddr) >> 12) & 0x3ff)
+#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
 
 /* Get PTE address accessors for each level. */
@@ -122,5 +126,5 @@
 #define PTE_WRITABLE_ARCH(p) \
 	((p)->writeable != 0)
-#define PTE_EXECUTABLE_ARCH(p)			1
+#define PTE_EXECUTABLE_ARCH(p)  1
 
 #ifndef __ASM__
@@ -144,5 +148,5 @@
 
 /** When bit on this position is 1, a reserved bit was set in page directory. */ 
-#define PFERR_CODE_RSVD		(1 << 3)	
+#define PFERR_CODE_RSVD		(1 << 3)
 
 /** Page Table Entry. */
Index: kernel/arch/ia32/include/smp/ap.h
===================================================================
--- kernel/arch/ia32/include/smp/ap.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/smp/ap.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia32	
+/** @addtogroup ia32
  * @{
  */
Index: kernel/arch/ia32/include/smp/apic.h
===================================================================
--- kernel/arch/ia32/include/smp/apic.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/smp/apic.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -49,63 +49,63 @@
 
 /** Delivery modes. */
-#define DELMOD_FIXED    0x0
-#define DELMOD_LOWPRI   0x1
-#define DELMOD_SMI      0x2
+#define DELMOD_FIXED    0x0U
+#define DELMOD_LOWPRI   0x1U
+#define DELMOD_SMI      0x2U
 /* 0x3 reserved */
-#define DELMOD_NMI      0x4
-#define DELMOD_INIT     0x5
-#define DELMOD_STARTUP  0x6
-#define DELMOD_EXTINT   0x7
+#define DELMOD_NMI      0x4U
+#define DELMOD_INIT     0x5U
+#define DELMOD_STARTUP  0x6U
+#define DELMOD_EXTINT   0x7U
 
 /** Destination modes. */
-#define DESTMOD_PHYS   0x0
-#define DESTMOD_LOGIC  0x1
+#define DESTMOD_PHYS   0x0U
+#define DESTMOD_LOGIC  0x1U
 
 /** Trigger Modes. */
-#define TRIGMOD_EDGE   0x0
-#define TRIGMOD_LEVEL  0x1
+#define TRIGMOD_EDGE   0x0U
+#define TRIGMOD_LEVEL  0x1U
 
 /** Levels. */
-#define LEVEL_DEASSERT  0x0
-#define LEVEL_ASSERT    0x1
+#define LEVEL_DEASSERT  0x0U
+#define LEVEL_ASSERT    0x1U
 
 /** Destination Shorthands. */
-#define SHORTHAND_NONE      0x0
-#define SHORTHAND_SELF      0x1
-#define SHORTHAND_ALL_INCL  0x2
-#define SHORTHAND_ALL_EXCL  0x3
+#define SHORTHAND_NONE      0x0U
+#define SHORTHAND_SELF      0x1U
+#define SHORTHAND_ALL_INCL  0x2U
+#define SHORTHAND_ALL_EXCL  0x3U
 
 /** Interrupt Input Pin Polarities. */
-#define POLARITY_HIGH  0x0
-#define POLARITY_LOW   0x1
+#define POLARITY_HIGH  0x0U
+#define POLARITY_LOW   0x1U
 
 /** Divide Values. (Bit 2 is always 0) */
-#define DIVIDE_2    0x0
-#define DIVIDE_4    0x1
-#define DIVIDE_8    0x2
-#define DIVIDE_16   0x3
-#define DIVIDE_32   0x8
-#define DIVIDE_64   0x9
-#define DIVIDE_128  0xa
-#define DIVIDE_1    0xb
+#define DIVIDE_2    0x0U
+#define DIVIDE_4    0x1U
+#define DIVIDE_8    0x2U
+#define DIVIDE_16   0x3U
+#define DIVIDE_32   0x8U
+#define DIVIDE_64   0x9U
+#define DIVIDE_128  0xaU
+#define DIVIDE_1    0xbU
 
 /** Timer Modes. */
-#define TIMER_ONESHOT   0x0
-#define TIMER_PERIODIC  0x1
+#define TIMER_ONESHOT   0x0U
+#define TIMER_PERIODIC  0x1U
 
 /** Delivery status. */
-#define DELIVS_IDLE     0x0
-#define DELIVS_PENDING  0x1
+#define DELIVS_IDLE     0x0U
+#define DELIVS_PENDING  0x1U
 
 /** Destination masks. */
-#define DEST_ALL  0xff
+#define DEST_ALL  0xffU
 
 /** Dest format models. */
-#define MODEL_FLAT     0xf
-#define MODEL_CLUSTER  0x0
+#define MODEL_FLAT     0xfU
+#define MODEL_CLUSTER  0x0U
 
 /** Interrupt Command Register. */
-#define ICRlo  (0x300 / sizeof(uint32_t))
-#define ICRhi  (0x310 / sizeof(uint32_t))
+#define ICRlo  (0x300U / sizeof(uint32_t))
+#define ICRhi  (0x310U / sizeof(uint32_t))
 
 typedef struct {
@@ -135,8 +135,8 @@
 
 /* End Of Interrupt. */
-#define EOI  (0x0b0 / sizeof(uint32_t))
+#define EOI  (0x0b0U / sizeof(uint32_t))
 
 /** Error Status Register. */
-#define ESR  (0x280 / sizeof(uint32_t))
+#define ESR  (0x280U / sizeof(uint32_t))
 
 typedef union {
@@ -157,5 +157,5 @@
 
 /* Task Priority Register */
-#define TPR  (0x080 / sizeof(uint32_t))
+#define TPR  (0x080U / sizeof(uint32_t))
 
 typedef union {
@@ -168,5 +168,5 @@
 
 /** Spurious-Interrupt Vector Register. */
-#define SVR  (0x0f0 / sizeof(uint32_t))
+#define SVR  (0x0f0U / sizeof(uint32_t))
 
 typedef union {
@@ -181,5 +181,5 @@
 
 /** Time Divide Configuration Register. */
-#define TDCR  (0x3e0 / sizeof(uint32_t))
+#define TDCR  (0x3e0U / sizeof(uint32_t))
 
 typedef union {
@@ -192,11 +192,11 @@
 
 /* Initial Count Register for Timer */
-#define ICRT  (0x380 / sizeof(uint32_t))
+#define ICRT  (0x380U / sizeof(uint32_t))
 
 /* Current Count Register for Timer */
-#define CCRT  (0x390 / sizeof(uint32_t))
+#define CCRT  (0x390U / sizeof(uint32_t))
 
 /** LVT Timer register. */
-#define LVT_Tm  (0x320 / sizeof(uint32_t))
+#define LVT_Tm  (0x320U / sizeof(uint32_t))
 
 typedef union {
@@ -214,6 +214,6 @@
 
 /** LVT LINT registers. */
-#define LVT_LINT0  (0x350 / sizeof(uint32_t))
-#define LVT_LINT1  (0x360 / sizeof(uint32_t))
+#define LVT_LINT0  (0x350U / sizeof(uint32_t))
+#define LVT_LINT1  (0x360U / sizeof(uint32_t))
 
 typedef union {
@@ -233,5 +233,5 @@
 
 /** LVT Error register. */
-#define LVT_Err  (0x370 / sizeof(uint32_t))
+#define LVT_Err  (0x370U / sizeof(uint32_t))
 
 typedef union {
@@ -248,5 +248,5 @@
 
 /** Local APIC ID Register. */
-#define L_APIC_ID  (0x020 / sizeof(uint32_t))
+#define L_APIC_ID  (0x020U / sizeof(uint32_t))
 
 typedef union {
@@ -259,13 +259,13 @@
 
 /** Local APIC Version Register */
-#define LAVR       (0x030 / sizeof(uint32_t))
-#define LAVR_Mask  0xff
-
-#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
-#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
-#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
+#define LAVR       (0x030U / sizeof(uint32_t))
+#define LAVR_Mask  0xffU
+
+#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0U) == 0x1U)
+#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0U) == 0x0U))
+#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14U)
 
 /** Logical Destination Register. */
-#define  LDR  (0x0d0 / sizeof(uint32_t))
+#define  LDR  (0x0d0U / sizeof(uint32_t))
 
 typedef union {
@@ -278,5 +278,5 @@
 
 /** Destination Format Register. */
-#define DFR  (0x0e0 / sizeof(uint32_t))
+#define DFR  (0x0e0U / sizeof(uint32_t))
 
 typedef union {
@@ -289,11 +289,11 @@
 
 /* IO APIC */
-#define IOREGSEL  (0x00 / sizeof(uint32_t))
-#define IOWIN     (0x10 / sizeof(uint32_t))
-
-#define IOAPICID   0x00
-#define IOAPICVER  0x01
-#define IOAPICARB  0x02
-#define IOREDTBL   0x10
+#define IOREGSEL  (0x00U / sizeof(uint32_t))
+#define IOWIN     (0x10U / sizeof(uint32_t))
+
+#define IOAPICID   0x00U
+#define IOAPICVER  0x01U
+#define IOAPICARB  0x02U
+#define IOREDTBL   0x10U
 
 /** I/O Register Select Register. */
Index: kernel/arch/ia32/include/types.h
===================================================================
--- kernel/arch/ia32/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -50,24 +50,9 @@
 } fncptr_t;
 
-#define PRIp "x"  /**< Format for uintptr_t. */
-#define PRIs "u"  /**< Format for size_t. */
-
-#define PRId8 "d"     /**< Format for int8_t. */
-#define PRId16 "d"    /**< Format for int16_t. */
-#define PRId32 "d"    /**< Format for int32_t. */
-#define PRId64 "lld"  /**< Format for int64_t. */
-#define PRIdn "d"     /**< Format for native_t. */
-
-#define PRIu8 "u"     /**< Format for uint8_t. */
-#define PRIu16 "u"    /**< Format for uint16_t. */
-#define PRIu32 "u"    /**< Format for uint32_t. */
-#define PRIu64 "llu"  /**< Format for uint64_t. */
-#define PRIun "u"     /**< Format for unative_t. */
-
-#define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
-#define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
-#define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
-#define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
-#define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
+#define PRIp   PRIx32  /**< Format for uintptr_t. */
+#define PRIs   PRIu32  /**< Format for size_t. */
+#define PRIdn  PRId32  /**< Format for native_t. */
+#define PRIun  PRIu32  /**< Format for unative_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/ia32/src/bios/bios.c
===================================================================
--- kernel/arch/ia32/src/bios/bios.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/bios/bios.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -36,5 +36,5 @@
 #include <typedefs.h>
 
-#define BIOS_EBDA_PTR  0x40e
+#define BIOS_EBDA_PTR  0x40eU
 
 uintptr_t ebda = 0;
@@ -43,5 +43,5 @@
 {
 	/* Copy the EBDA address out from BIOS Data Area */
-	ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10;
+	ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10U;
 }
 
Index: kernel/arch/ia32/src/boot/memmap.c
===================================================================
--- kernel/arch/ia32/src/boot/memmap.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/boot/memmap.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -35,5 +35,5 @@
 #include <arch/boot/memmap.h>
 
-uint8_t e820counter = 0xff;
+uint8_t e820counter = 0xffU;
 e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
 
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -49,11 +49,11 @@
  * Contains only non-MP-Specification specific SMP code.
  */
-#define AMD_CPUID_EBX  0x68747541
-#define AMD_CPUID_ECX  0x444d4163
-#define AMD_CPUID_EDX  0x69746e65
+#define AMD_CPUID_EBX  UINT32_C(0x68747541)
+#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
+#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
 
-#define INTEL_CPUID_EBX  0x756e6547
-#define INTEL_CPUID_ECX  0x6c65746e
-#define INTEL_CPUID_EDX  0x49656e69
+#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
+#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
+#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
 
 
@@ -140,19 +140,19 @@
 		if ((info.cpuid_ebx == AMD_CPUID_EBX)
 		    && (info.cpuid_ecx == AMD_CPUID_ECX)
-			&& (info.cpuid_edx == AMD_CPUID_EDX))
+		    && (info.cpuid_edx == AMD_CPUID_EDX))
 			CPU->arch.vendor = VendorAMD;
 		
 		/*
 		 * Check for Intel processor.
-		 */		
+		 */
 		if ((info.cpuid_ebx == INTEL_CPUID_EBX)
 		    && (info.cpuid_ecx == INTEL_CPUID_ECX)
-			&& (info.cpuid_edx == INTEL_CPUID_EDX))
+		    && (info.cpuid_edx == INTEL_CPUID_EDX))
 			CPU->arch.vendor = VendorIntel;
 		
 		cpuid(INTEL_CPUID_STANDARD, &info);
-		CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
-		CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
-		CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;						
+		CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU;
+		CPU->arch.model = (info.cpuid_eax >> 4) & 0x0fU;
+		CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0fU;
 	}
 }
Index: kernel/arch/ia32/src/debug/stacktrace.c
===================================================================
--- kernel/arch/ia32/src/debug/stacktrace.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/debug/stacktrace.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -37,6 +37,6 @@
 #include <typedefs.h>
 
-#define FRAME_OFFSET_FP_PREV	0
-#define FRAME_OFFSET_RA		1
+#define FRAME_OFFSET_FP_PREV  0
+#define FRAME_OFFSET_RA       1
 
 bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx)
Index: kernel/arch/ia32/src/drivers/i8254.c
===================================================================
--- kernel/arch/ia32/src/drivers/i8254.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/drivers/i8254.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -54,6 +54,6 @@
 #include <ddi/device.h>
 
-#define CLK_PORT1  ((ioport8_t *) 0x40)
-#define CLK_PORT4  ((ioport8_t *) 0x43)
+#define CLK_PORT1  ((ioport8_t *) 0x40U)
+#define CLK_PORT4  ((ioport8_t *) 0x43U)
 
 #define CLK_CONST     1193180
Index: kernel/arch/ia32/src/drivers/i8259.c
===================================================================
--- kernel/arch/ia32/src/drivers/i8259.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/drivers/i8259.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -121,6 +121,6 @@
 void pic_eoi(void)
 {
-	pio_write_8((ioport8_t *)0x20, 0x20);
-	pio_write_8((ioport8_t *)0xa0, 0x20);
+	pio_write_8((ioport8_t *) 0x20, 0x20);
+	pio_write_8((ioport8_t *) 0xa0, 0x20);
 }
 
Index: kernel/arch/ia32/src/drivers/vesa.c
===================================================================
--- kernel/arch/ia32/src/drivers/vesa.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/drivers/vesa.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -70,5 +70,5 @@
 bool vesa_init(void)
 {
-	if ((vesa_width == 0xffff) || (vesa_height == 0xffff))
+	if ((vesa_width == 0xffffU) || (vesa_height == 0xffffU))
 		return false;
 	
Index: kernel/arch/ia32/src/mm/frame.c
===================================================================
--- kernel/arch/ia32/src/mm/frame.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/mm/frame.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -44,9 +44,8 @@
 #include <align.h>
 #include <macros.h>
-
 #include <print.h>
 
-#define PHYSMEM_LIMIT32  0x07c000000ull
-#define PHYSMEM_LIMIT64  0x200000000ull
+#define PHYSMEM_LIMIT32  UINT64_C(0x07c000000)
+#define PHYSMEM_LIMIT64  UINT64_C(0x200000000)
 
 size_t hardcoded_unmapped_ktext_size = 0;
Index: kernel/arch/ia32/src/smp/apic.c
===================================================================
--- kernel/arch/ia32/src/smp/apic.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/smp/apic.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -72,6 +72,6 @@
  *
  */
-volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
-volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
+volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
+volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
 
 uint32_t apic_id_mask = 0;
@@ -184,5 +184,5 @@
 	 * Other interrupts will be forwarded to the lowest priority CPU.
 	 */
-	io_apic_disable_irqs(0xffff);
+	io_apic_disable_irqs(0xffffU);
 	
 	irq_initialize(&l_apic_timer_irq);
Index: kernel/arch/ia32/src/smp/mps.c
===================================================================
--- kernel/arch/ia32/src/smp/mps.c	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia32/src/smp/mps.c	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -52,6 +52,6 @@
  */
 
-#define FS_SIGNATURE  0x5f504d5f
-#define CT_SIGNATURE  0x504d4350
+#define FS_SIGNATURE  UINT32_C(0x5f504d5f)
+#define CT_SIGNATURE  UINT32_C(0x504d4350)
 
 static struct mps_fs *fs;
Index: kernel/arch/ia64/include/types.h
===================================================================
--- kernel/arch/ia64/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ia64/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -52,24 +52,9 @@
 } __attribute__((may_alias)) fncptr_t;
 
-#define PRIp "lx"  /**< Format for uintptr_t. */
-#define PRIs "lu"  /**< Format for size_t. */
-
-#define PRId8 "d"    /**< Format for int8_t. */
-#define PRId16 "d"   /**< Format for int16_t. */
-#define PRId32 "d"   /**< Format for int32_t. */
-#define PRId64 "ld"  /**< Format for int64_t. */
-#define PRIdn "d"    /**< Format for native_t. */
-
-#define PRIu8 "u"    /**< Format for uint8_t. */
-#define PRIu16 "u"   /**< Format for uint16_t. */
-#define PRIu32 "u"   /**< Format for uint32_t. */
-#define PRIu64 "lu"  /**< Format for uint64_t. */
-#define PRIun "u"    /**< Format for unative_t. */
-
-#define PRIx8 "x"    /**< Format for hexadecimal (u)int8_t. */
-#define PRIx16 "x"   /**< Format for hexadecimal (u)int16_t. */
-#define PRIx32 "x"   /**< Format for hexadecimal (u)uint32_t. */
-#define PRIx64 "lx"  /**< Format for hexadecimal (u)int64_t. */
-#define PRIxn "x"    /**< Format for hexadecimal (u)native_t. */
+#define PRIp   PRIx64  /**< Format for uintptr_t. */
+#define PRIs   PRIu64  /**< Format for size_t. */
+#define PRIdn  PRId64  /**< Format for native_t. */
+#define PRIun  PRIu64  /**< Format for unative_t. */
+#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/mips32/include/types.h
===================================================================
--- kernel/arch/mips32/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/mips32/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -50,24 +50,9 @@
 } fncptr_t;
 
-#define PRIp "x"  /**< Format for uintptr_t. */
-#define PRIs "u"  /**< Format for size_t. */
-
-#define PRId8 "d"     /**< Format for int8_t. */
-#define PRId16 "d"    /**< Format for int16_t. */
-#define PRId32 "ld"   /**< Format for int32_t. */
-#define PRId64 "lld"  /**< Format for int64_t. */
-#define PRIdn "d"     /**< Format for native_t. */
-
-#define PRIu8 "u"     /**< Format for uint8_t. */
-#define PRIu16 "u"    /**< Format for uint16_t. */
-#define PRIu32 "u"    /**< Format for uint32_t. */
-#define PRIu64 "llu"  /**< Format for uint64_t. */
-#define PRIun "u"     /**< Format for unative_t. */
-
-#define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
-#define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
-#define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
-#define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
-#define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
+#define PRIp   PRIx32  /**< Format for uintptr_t. */
+#define PRIs   PRIu32  /**< Format for size_t. */
+#define PRIdn  PRId32  /**< Format for native_t. */
+#define PRIun  PRIu32  /**< Format for unative_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/ppc32/include/types.h
===================================================================
--- kernel/arch/ppc32/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/ppc32/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -50,26 +50,9 @@
 } fncptr_t;
 
-/** Formats for uintptr_t, size_t */
-#define PRIp  "x"
-#define PRIs  "u"
-
-/** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
-#define PRId8   "d"
-#define PRId16  "d"
-#define PRId32  "d"
-#define PRId64  "lld"
-#define PRIdn   "d"
-
-#define PRIu8   "u"
-#define PRIu16  "u"
-#define PRIu32  "u"
-#define PRIu64  "llu"
-#define PRIun   "u"
-
-#define PRIx8   "x"
-#define PRIx16  "x"
-#define PRIx32  "x"
-#define PRIx64  "llx"
-#define PRIxn   "x"
+#define PRIp   PRIx32  /**< Format for uintptr_t. */
+#define PRIs   PRIu32  /**< Format for size_t. */
+#define PRIdn  PRId32  /**< Format for native_t. */
+#define PRIun  PRIu32  /**< Format for unative_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
 
 #endif
Index: kernel/arch/sparc64/include/types.h
===================================================================
--- kernel/arch/sparc64/include/types.h	(revision 8b3bff5d1aa2243a615a88d37b89521257235410)
+++ kernel/arch/sparc64/include/types.h	(revision 85369b111f458fd417a10d0c8caeffa9462adf19)
@@ -52,26 +52,9 @@
 typedef uint8_t asi_t;
 
-/** Formats for uintptr_t, size_t */
-#define PRIp  "llx"
-#define PRIs  "llu"
-
-/** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
-#define PRId8   "d"
-#define PRId16  "d"
-#define PRId32  "d"
-#define PRId64  "lld"
-#define PRIdn   "lld"
-
-#define PRIu8   "u"
-#define PRIu16  "u"
-#define PRIu32  "u"
-#define PRIu64  "llu"
-#define PRIun   "llu"
-
-#define PRIx8   "x"
-#define PRIx16  "x"
-#define PRIx32  "x"
-#define PRIx64  "llx"
-#define PRIxn   "llx"
+#define PRIp   PRIx64  /**< Format for uintptr_t. */
+#define PRIs   PRIu64  /**< Format for size_t. */
+#define PRIdn  PRId64  /**< Format for native_t. */
+#define PRIun  PRIu64  /**< Format for unative_t. */
+#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
 
 #endif
