Changeset 81716eb in mainline for uspace/drv


Ignore:
Timestamp:
2012-04-08T17:53:15Z (14 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c5bff3c
Parents:
1b90e90 (diff), f3378ba (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Mainline changes.

Location:
uspace/drv
Files:
1 added
1 deleted
16 edited
5 moved

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/isa/isa.c

    r1b90e90 r81716eb  
    6666#include <ops/hw_res.h>
    6767
    68 #include <devman.h>
    69 #include <ipc/devman.h>
    7068#include <device/hw_res.h>
    7169

  • uspace/drv/bus/usb/ehci/Makefile

    r1b90e90 r81716eb  
    4343SOURCES = \
    4444        main.c \
    45         pci.c
     45        res.c
    4646
    4747include $(USPACE_PREFIX)/Makefile.common

  • uspace/drv/bus/usb/ehci/main.c

    r1b90e90 r81716eb  
    4444#include <usb/host/hcd.h>
    4545
    46 #include "pci.h"
     46#include "res.h"
    4747
    4848#define NAME "ehci"
    … …  
    8181        int irq = 0;
    8282
    83         int ret = pci_get_my_registers(device, &reg_base, &reg_size, &irq);
     83        int ret = get_my_registers(device, &reg_base, &reg_size, &irq);
    8484        CHECK_RET_RETURN(ret,
    8585            "Failed to get memory addresses for %" PRIun ": %s.\n",
    … …  
    8888            reg_base, reg_size, irq);
    8989
    90         ret = pci_disable_legacy(device, reg_base, reg_size, irq);
     90        ret = disable_legacy(device, reg_base, reg_size);
    9191        CHECK_RET_RETURN(ret,
    9292            "Failed to disable legacy USB: %s.\n", str_error(ret));

  • uspace/drv/bus/usb/ehci/res.h

    r1b90e90 r81716eb  
    3838#include <ddf/driver.h>
    3939
    40 int pci_get_my_registers(const ddf_dev_t *, uintptr_t *, size_t *, int *);
    41 int pci_enable_interrupts(const ddf_dev_t *);
    42 int pci_disable_legacy(const ddf_dev_t *, uintptr_t, size_t, int);
     40int get_my_registers(const ddf_dev_t *, uintptr_t *, size_t *, int *);
     41int enable_interrupts(const ddf_dev_t *);
     42int disable_legacy(const ddf_dev_t *, uintptr_t, size_t);
    4343
    4444#endif

  • uspace/drv/bus/usb/ohci/Makefile

    r1b90e90 r81716eb  
    5050        ohci_batch.c \
    5151        ohci_endpoint.c \
    52         pci.c \
     52        res.c \
    5353        root_hub.c \
    5454        hw_struct/endpoint_descriptor.c \

  • uspace/drv/bus/usb/ohci/hw_struct/hcca.h

    r1b90e90 r81716eb  
    5454        uint32_t done_head;
    5555        /** Padding to make the size 256B */
    56         uint32_t reserved[29];
    57 } __attribute__((packed, aligned)) hcca_t;
     56        uint32_t reserved[30];
     57} hcca_t;
    5858
    5959/** Allocate properly aligned structure.

  • uspace/drv/bus/usb/ohci/ohci.c

    r1b90e90 r81716eb  
    4242
    4343#include "ohci.h"
    44 #include "pci.h"
     44#include "res.h"
    4545#include "hc.h"
    4646
    … …  
    180180        int irq = 0;
    181181
    182         ret = pci_get_my_registers(device, &reg_base, &reg_size, &irq);
     182        ret = get_my_registers(device, &reg_base, &reg_size, &irq);
    183183        CHECK_RET_DEST_FREE_RETURN(ret,
    184184            "Failed to get register memory addresses for %" PRIun ": %s.\n",
    … …  
    211211        /* Try to enable interrupts */
    212212        bool interrupts = false;
    213         ret = pci_enable_interrupts(device);
     213        ret = enable_interrupts(device);
    214214        if (ret != EOK) {
    215215                usb_log_warning("Failed to enable interrupts: %s."

  • uspace/drv/bus/usb/ohci/res.c

    r1b90e90 r81716eb  
    3838#include <errno.h>
    3939#include <assert.h>
    40 #include <as.h>
    4140#include <devman.h>
    42 #include <ddi.h>
    43 #include <libarch/ddi.h>
    4441#include <device/hw_res_parsed.h>
    4542
    4643#include <usb/debug.h>
    47 #include <pci_dev_iface.h>
    4844
    49 #include "pci.h"
     45#include "res.h"
    5046
    5147/** Get address of registers and IRQ for given device.
    … …  
    5753 * @return Error code.
    5854 */
    59 int pci_get_my_registers(ddf_dev_t *dev,
     55int get_my_registers(const ddf_dev_t *dev,
    6056    uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
    6157{
    … …  
    9894 * @return Error code.
    9995 */
    100 int pci_enable_interrupts(ddf_dev_t *device)
     96int enable_interrupts(const ddf_dev_t *device)
    10197{
    10298        async_sess_t *parent_sess =
    … …  
    106102                return ENOMEM;
    107103       
    108         bool enabled = hw_res_enable_interrupt(parent_sess);
     104        const bool enabled = hw_res_enable_interrupt(parent_sess);
    109105        async_hangup(parent_sess);
    110106       

  • uspace/drv/bus/usb/ohci/res.h

    r1b90e90 r81716eb  
    3232 * PCI related functions needed by OHCI driver.
    3333 */
    34 #ifndef DRV_OHCI_PCI_H
    35 #define DRV_OHCI_PCI_H
     34#ifndef DRV_OHCI_RES_H
     35#define DRV_OHCI_RES_H
    3636
    3737#include <ddf/driver.h>
    3838
    39 int pci_get_my_registers(ddf_dev_t *, uintptr_t *, size_t *, int *);
    40 int pci_enable_interrupts(ddf_dev_t *);
    41 int pci_disable_legacy(ddf_dev_t *);
     39int get_my_registers(const ddf_dev_t *, uintptr_t *, size_t *, int *);
     40int enable_interrupts(const ddf_dev_t *);
    4241
    4342#endif

  • uspace/drv/bus/usb/uhci/Makefile

    r1b90e90 r81716eb  
    4444        hc.c \
    4545        main.c \
    46         pci.c \
     46        res.c \
    4747        root_hub.c \
    4848        transfer_list.c \

  • uspace/drv/bus/usb/uhci/res.c

    r1b90e90 r81716eb  
    3939#include <devman.h>
    4040#include <device/hw_res_parsed.h>
     41#include <device/pci.h>
    4142
    42 #include <usb/debug.h>
    43 #include <pci_dev_iface.h>
    44 
    45 #include "pci.h"
     43#include "res.h"
    4644
    4745/** Get I/O address of registers and IRQ for given device.
    … …  
    5351 * @return Error code.
    5452 */
    55 int pci_get_my_registers(const ddf_dev_t *dev,
     53int get_my_registers(const ddf_dev_t *dev,
    5654    uintptr_t *io_reg_address, size_t *io_reg_size, int *irq_no)
    5755{
    5856        assert(dev);
    59         assert(io_reg_address);
    60         assert(io_reg_size);
    61         assert(irq_no);
    6257
    6358        async_sess_t *parent_sess =
    … …  
    9792 * @return Error code.
    9893 */
    99 int pci_enable_interrupts(const ddf_dev_t *device)
     94int enable_interrupts(const ddf_dev_t *device)
    10095{
    10196        async_sess_t *parent_sess =
    … …  
    116111 * @return Error code.
    117112 */
    118 int pci_disable_legacy(const ddf_dev_t *device)
     113int disable_legacy(const ddf_dev_t *device)
    119114{
    120115        assert(device);
    121116
    122         async_sess_t *parent_sess =
    123             devman_parent_device_connect(EXCHANGE_SERIALIZE, device->handle,
    124             IPC_FLAG_BLOCKING);
     117        async_sess_t *parent_sess = devman_parent_device_connect(
     118            EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING);
    125119        if (!parent_sess)
    126120                return ENOMEM;
    127121
    128         /* See UHCI design guide for these values p.45,
    129          * write all WC bits in USB legacy register */
    130         const sysarg_t address = 0xc0;
    131         const sysarg_t value = 0xaf00;
     122        /* See UHCI design guide page 45 for these values.
     123         * Write all WC bits in USB legacy register */
     124        const int rc = pci_config_space_write_16(parent_sess, 0xc0, 0xaf00);
    132125
    133         async_exch_t *exch = async_exchange_begin(parent_sess);
    134 
    135         const int rc = async_req_3_0(exch, DEV_IFACE_ID(PCI_DEV_IFACE),
    136             IPC_M_CONFIG_SPACE_WRITE_16, address, value);
    137 
    138         async_exchange_end(exch);
    139126        async_hangup(parent_sess);
    140 
    141127        return rc;
    142128}

  • uspace/drv/bus/usb/uhci/res.h

    r1b90e90 r81716eb  
    3838#include <ddf/driver.h>
    3939
    40 int pci_get_my_registers(const ddf_dev_t *, uintptr_t *, size_t *, int *);
    41 int pci_enable_interrupts(const ddf_dev_t *);
    42 int pci_disable_legacy(const ddf_dev_t *);
     40int get_my_registers(const ddf_dev_t *, uintptr_t *, size_t *, int *);
     41int enable_interrupts(const ddf_dev_t *);
     42int disable_legacy(const ddf_dev_t *);
    4343
    4444#endif

  • uspace/drv/bus/usb/uhci/uhci.c

    r1b90e90 r81716eb  
    4141
    4242#include "uhci.h"
    43 #include "pci.h"
    44 
     43
     44#include "res.h"
    4545#include "hc.h"
    4646#include "root_hub.h"
    … …  
    4949 * and USB root hub */
    5050typedef struct uhci {
    51         /** Pointer to DDF represenation of UHCI host controller */
     51        /** Pointer to DDF representation of UHCI host controller */
    5252        ddf_fun_t *hc_fun;
    53         /** Pointer to DDF represenation of UHCI root hub */
     53        /** Pointer to DDF representation of UHCI root hub */
    5454        ddf_fun_t *rh_fun;
    5555
    56         /** Internal driver's represenation of UHCI host controller */
     56        /** Internal driver's representation of UHCI host controller */
    5757        hc_t hc;
    58         /** Internal driver's represenation of UHCI root hub */
     58        /** Internal driver's representation of UHCI root hub */
    5959        rh_t rh;
    6060} uhci_t;
    … …  
    187187        int irq = 0;
    188188
    189         ret = pci_get_my_registers(device, &reg_base, &reg_size, &irq);
     189        ret = get_my_registers(device, &reg_base, &reg_size, &irq);
    190190        CHECK_RET_DEST_FREE_RETURN(ret,
    191191            "Failed to get I/O addresses for %" PRIun ": %s.\n",
    … …  
    194194            (void *) reg_base, reg_size, irq);
    195195
    196         ret = pci_disable_legacy(device);
     196        ret = disable_legacy(device);
    197197        CHECK_RET_DEST_FREE_RETURN(ret,
    198198            "Failed to disable legacy USB: %s.\n", str_error(ret));
    … …  
    220220
    221221        bool interrupts = false;
    222         ret = pci_enable_interrupts(device);
     222        ret = enable_interrupts(device);
    223223        if (ret != EOK) {
    224224                usb_log_warning("Failed to enable interrupts: %s."

  • uspace/drv/bus/usb/uhcirh/port.c

    r1b90e90 r81716eb  
    3737#include <str_error.h>
    3838#include <async.h>
    39 #include <devman.h>
    4039
    4140#include <usb/usb.h>    /* usb_address_t */

  • uspace/drv/bus/usb/usbhub/port.c

    r1b90e90 r81716eb  
    3535
    3636#include <bool.h>
    37 #include <devman.h>
    3837#include <errno.h>
    3938#include <str_error.h>

  • uspace/drv/char/ns8250/ns8250.c

    r1b90e90 r81716eb  
    7474#define DLAB_MASK (1 << 7)
    7575
     76/** Interrupt Enable Register definition. */
     77#define NS8250_IER_RXREADY      (1 << 0)
     78#define NS8250_IER_THRE         (1 << 1)
     79#define NS8250_IER_RXSTATUS     (1 << 2)
     80#define NS8250_IER_MODEM_STATUS (1 << 3)
     81
     82/** Interrupt ID Register definition. */
     83#define NS8250_IID_ACTIVE       (1 << 0)
     84
     85/** FIFO Control Register definition. */
     86#define NS8250_FCR_FIFOENABLE   (1 << 0)
     87#define NS8250_FCR_RXFIFORESET  (1 << 1)
     88#define NS8250_FCR_TXFIFORESET  (1 << 2)
     89#define NS8250_FCR_DMAMODE      (1 << 3)
     90#define NS8250_FCR_RXTRIGGERLOW (1 << 6)
     91#define NS8250_FCR_RXTRIGGERHI  (1 << 7)
     92
     93/** Line Control Register definition. */
     94#define NS8250_LCR_STOPBITS     (1 << 2)
     95#define NS8250_LCR_PARITY       (1 << 3)
     96#define NS8250_LCR_SENDBREAK    (1 << 6)
     97#define NS8250_LCR_DLAB         (1 << 7)
     98
     99/** Modem Control Register definition. */
     100#define NS8250_MCR_DTR          (1 << 0)
     101#define NS8250_MCR_RTS          (1 << 1)
     102#define NS8250_MCR_OUT1         (1 << 2)
     103#define NS8250_MCR_OUT2         (1 << 3)
     104#define NS8250_MCR_LOOPBACK     (1 << 4)
     105#define NS8250_MCR_ALL          (0x1f)
     106
     107/** Line Status Register definition. */
     108#define NS8250_LSR_RXREADY      (1 << 0)
     109#define NS8250_LSR_OE           (1 << 1)
     110#define NS8250_LSR_PE           (1 << 2)
     111#define NS8250_LSR_FE           (1 << 3)
     112#define NS8250_LSR_BREAK        (1 << 4)
     113#define NS8250_LSR_THRE         (1 << 5)
     114#define NS8250_LSR_TSE          (1 << 6)
     115
     116/** Modem Status Register definition. */
     117#define NS8250_MSR_DELTACTS     (1 << 0)
     118#define NS8250_MSR_DELTADSR     (1 << 1)
     119#define NS8250_MSR_RITRAILING   (1 << 2)
     120#define NS8250_MSR_DELTADCD     (1 << 3)
     121#define NS8250_MSR_CTS          (1 << 4)
     122#define NS8250_MSR_DSR          (1 << 5)
     123#define NS8250_MSR_RI           (1 << 6)
     124#define NS8250_MSR_DCD          (1 << 7)
     125#define NS8250_MSR_SIGNALS      (NS8250_MSR_CTS | NS8250_MSR_DSR \
     126    | NS8250_MSR_RI | NS8250_MSR_DCD)
     127
    76128/** Obtain soft-state structure from function node */
    77129#define NS8250(fnode) ((ns8250_t *) ((fnode)->dev->driver_data))
    … …  
    96148} stop_bit_t;
    97149
     150/** 8250 UART registers layout. */
     151typedef struct {
     152        ioport8_t data;         /**< Data register. */
     153        ioport8_t ier;          /**< Interrupt Enable Reg. */
     154        ioport8_t iid;          /**< Interrupt ID Reg. */
     155        ioport8_t lcr;          /**< Line Control Reg. */
     156        ioport8_t mcr;          /**< Modem Control Reg. */
     157        ioport8_t lsr;          /**< Line Status Reg. */
     158        ioport8_t msr;          /**< Modem Status Reg. */
     159} ns8250_regs_t;
     160
    98161/** The driver data for the serial port devices. */
    99162typedef struct ns8250 {
    … …  
    102165        /** DDF function node */
    103166        ddf_fun_t *fun;
     167        /** I/O registers **/
     168        ns8250_regs_t *regs;
    104169        /** Is there any client conntected to the device? */
    105170        bool client_connected;
    … …  
    124189 *                      otherwise.
    125190 */
    126 static bool ns8250_received(ioport8_t *port)
    127 {
    128         return (pio_read_8(port + 5) & 1) != 0;
     191static bool ns8250_received(ns8250_regs_t *regs)
     192{
     193        return (pio_read_8(&regs->lsr) & NS8250_LSR_RXREADY) != 0;
    129194}
    130195
    … …  
    134199 * @return              The data read.
    135200 */
    136 static uint8_t ns8250_read_8(ioport8_t *port)
    137 {
    138         return pio_read_8(port);
     201static uint8_t ns8250_read_8(ns8250_regs_t *regs)
     202{
     203        return pio_read_8(&regs->data);
    139204}
    140205
    … …  
    143208 * @param port          The base address of the serial port device's ports.
    144209 */
    145 static bool is_transmit_empty(ioport8_t *port)
    146 {
    147         return (pio_read_8(port + 5) & 0x20) != 0;
     210static bool is_transmit_empty(ns8250_regs_t *regs)
     211{
     212        return (pio_read_8(&regs->lsr) & NS8250_LSR_THRE) != 0;
    148213}
    149214
    … …  
    153218 * @param c             The character to be written to the serial port device.
    154219 */
    155 static void ns8250_write_8(ioport8_t *port, uint8_t c)
    156 {
    157         while (!is_transmit_empty(port))
     220static void ns8250_write_8(ns8250_regs_t *regs, uint8_t c)
     221{
     222        while (!is_transmit_empty(regs))
    158223                ;
    159224       
    160         pio_write_8(port, c);
     225        pio_write_8(&regs->data, c);
    161226}
    162227
    … …  
    193258{
    194259        fibril_mutex_lock(&ns->mutex);
    195         ns8250_write_8(ns->port, c);
     260        ns8250_write_8(ns->regs, c);
    196261        fibril_mutex_unlock(&ns->mutex);
    197262}
    … …  
    212277                ns8250_putchar(ns, (uint8_t) buf[idx]);
    213278       
    214         return 0;
     279        return count;
    215280}
    216281
    … …  
    266331                return false;
    267332        }
     333
     334        ns->regs = (ns8250_regs_t *)ns->port;
    268335       
    269336        return true;
    … …  
    279346        ddf_msg(LVL_DEBUG, "ns8250_dev_probe %s", ns->dev->name);
    280347       
    281         ioport8_t *port_addr = ns->port;
    282348        bool res = true;
    283349        uint8_t olddata;
    284350       
    285         olddata = pio_read_8(port_addr + 4);
    286        
    287         pio_write_8(port_addr + 4, 0x10);
    288         if (pio_read_8(port_addr + 6) & 0xf0)
     351        olddata = pio_read_8(&ns->regs->mcr);
     352       
     353        pio_write_8(&ns->regs->mcr, NS8250_MCR_LOOPBACK);
     354        if (pio_read_8(&ns->regs->msr) & NS8250_MSR_SIGNALS)
    289355                res = false;
    290356       
    291         pio_write_8(port_addr + 4, 0x1f);
    292         if ((pio_read_8(port_addr + 6) & 0xf0) != 0xf0)
     357        pio_write_8(&ns->regs->mcr, NS8250_MCR_ALL);
     358        if ((pio_read_8(&ns->regs->msr) & NS8250_MSR_SIGNALS)
     359            != NS8250_MSR_SIGNALS)
    293360                res = false;
    294361       
    295         pio_write_8(port_addr + 4, olddata);
     362        pio_write_8(&ns->regs->mcr, olddata);
    296363       
    297364        if (!res) {
    … …  
    390457 * @param port          The base address of the serial port device's ports.
    391458 */
    392 static inline void ns8250_port_interrupts_enable(ioport8_t *port)
    393 {
    394         pio_write_8(port + 1, 0x1);     /* Interrupt when data received. */
    395         pio_write_8(port + 4, 0xB);
     459static inline void ns8250_port_interrupts_enable(ns8250_regs_t *regs)
     460{
     461        /* Interrupt when data received. */
     462        pio_write_8(&regs->ier, NS8250_IER_RXREADY);
     463        pio_write_8(&regs->mcr, NS8250_MCR_DTR | NS8250_MCR_RTS
     464            | NS8250_MCR_OUT2);
    396465}
    397466
    … …  
    400469 * @param port          The base address of the serial port device's ports
    401470 */
    402 static inline void ns8250_port_interrupts_disable(ioport8_t *port)
    403 {
    404         pio_write_8(port + 1, 0x0);     /* Disable all interrupts. */
     471static inline void ns8250_port_interrupts_disable(ns8250_regs_t *regs)
     472{
     473        pio_write_8(&regs->ier, 0x0);   /* Disable all interrupts. */
    405474}
    406475
    … …  
    431500
    432501        /* Enable interrupt on the serial port. */
    433         ns8250_port_interrupts_enable(ns->port);
     502        ns8250_port_interrupts_enable(ns->regs);
    434503       
    435504        return EOK;
    … …  
    443512 * @param port          The base address of the serial port device's ports.
    444513 */
    445 static inline void enable_dlab(ioport8_t *port)
    446 {
    447         uint8_t val = pio_read_8(port + 3);
    448         pio_write_8(port + 3, val | DLAB_MASK);
     514static inline void enable_dlab(ns8250_regs_t *regs)
     515{
     516        uint8_t val = pio_read_8(&regs->lcr);
     517        pio_write_8(&regs->lcr, val | NS8250_LCR_DLAB);
    449518}
    450519
    … …  
    453522 * @param port          The base address of the serial port device's ports.
    454523 */
    455 static inline void clear_dlab(ioport8_t *port)
    456 {
    457         uint8_t val = pio_read_8(port + 3);
    458         pio_write_8(port + 3, val & (~DLAB_MASK));
     524static inline void clear_dlab(ns8250_regs_t *regs)
     525{
     526        uint8_t val = pio_read_8(&regs->lcr);
     527        pio_write_8(&regs->lcr, val & (~NS8250_LCR_DLAB));
    459528}
    460529
    … …  
    466535 *                      if the specified baud_rate is not valid).
    467536 */
    468 static int ns8250_port_set_baud_rate(ioport8_t *port, unsigned int baud_rate)
     537static int ns8250_port_set_baud_rate(ns8250_regs_t *regs, unsigned int baud_rate)
    469538{
    470539        uint16_t divisor;
    … …  
    482551       
    483552        /* Enable DLAB to be able to access baud rate divisor. */
    484         enable_dlab(port);
     553        enable_dlab(regs);
    485554       
    486555        /* Set divisor low byte. */
    487         pio_write_8(port + 0, div_low);
     556        pio_write_8(&regs->data, div_low);
    488557        /* Set divisor high byte. */
    489         pio_write_8(port + 1, div_high);
    490        
    491         clear_dlab(port);
     558        pio_write_8(&regs->ier, div_high);
     559       
     560        clear_dlab(regs);
    492561       
    493562        return EOK;
    … …  
    499568 * @param baud_rate     The ouput parameter to which the baud rate is stored.
    500569 */
    501 static unsigned int ns8250_port_get_baud_rate(ioport8_t *port)
     570static unsigned int ns8250_port_get_baud_rate(ns8250_regs_t *regs)
    502571{
    503572        uint16_t divisor;
    … …  
    505574       
    506575        /* Enable DLAB to be able to access baud rate divisor. */
    507         enable_dlab(port);
     576        enable_dlab(regs);
    508577       
    509578        /* Get divisor low byte. */
    510         div_low = pio_read_8(port + 0);
     579        div_low = pio_read_8(&regs->data);
    511580        /* Get divisor high byte. */
    512         div_high = pio_read_8(port + 1);
    513        
    514         clear_dlab(port);
     581        div_high = pio_read_8(&regs->ier);
     582       
     583        clear_dlab(regs);
    515584       
    516585        divisor = (div_high << 8) | div_low;
    … …  
    525594 * @param stop_bits     The number of stop bits used (one or two).
    526595 */
    527 static void ns8250_port_get_com_props(ioport8_t *port, unsigned int *parity,
     596static void ns8250_port_get_com_props(ns8250_regs_t *regs, unsigned int *parity,
    528597    unsigned int *word_length, unsigned int *stop_bits)
    529598{
    530599        uint8_t val;
    531600       
    532         val = pio_read_8(port + 3);
    533         *parity = ((val >> 3) & 7);
     601        val = pio_read_8(&regs->lcr);
     602        *parity = ((val >> NS8250_LCR_PARITY) & 7);
    534603       
    535604        switch (val & 3) {
    … …  
    548617        }
    549618       
    550         if ((val >> 2) & 1)
     619        if ((val >> NS8250_LCR_STOPBITS) & 1)
    551620                *stop_bits = 2;
    552621        else
    … …  
    562631 *                      is invalid.
    563632 */
    564 static int ns8250_port_set_com_props(ioport8_t *port, unsigned int parity,
     633static int ns8250_port_set_com_props(ns8250_regs_t *regs, unsigned int parity,
    565634    unsigned int word_length, unsigned int stop_bits)
    566635{
    … …  
    586655        switch (stop_bits) {
    587656        case 1:
    588                 val |= ONE_STOP_BIT << 2;
     657                val |= ONE_STOP_BIT << NS8250_LCR_STOPBITS;
    589658                break;
    590659        case 2:
    591                 val |= TWO_STOP_BITS << 2;
     660                val |= TWO_STOP_BITS << NS8250_LCR_STOPBITS;
    592661                break;
    593662        default:
    … …  
    601670        case SERIAL_MARK_PARITY:
    602671        case SERIAL_SPACE_PARITY:
    603                 val |= parity << 3;
     672                val |= parity << NS8250_LCR_PARITY;
    604673                break;
    605674        default:
    … …  
    607676        }
    608677       
    609         pio_write_8(port + 3, val);
     678        pio_write_8(&regs->lcr, val);
    610679       
    611680        return EOK;
    … …  
    620689static void ns8250_initialize_port(ns8250_t *ns)
    621690{
    622         ioport8_t *port = ns->port;
    623        
    624691        /* Disable interrupts. */
    625         ns8250_port_interrupts_disable(port);
     692        ns8250_port_interrupts_disable(ns->regs);
    626693        /* Set baud rate. */
    627         ns8250_port_set_baud_rate(port, 38400);
     694        ns8250_port_set_baud_rate(ns->regs, 38400);
    628695        /* 8 bits, no parity, two stop bits. */
    629         ns8250_port_set_com_props(port, SERIAL_NO_PARITY, 8, 2);
     696        ns8250_port_set_com_props(ns->regs, SERIAL_NO_PARITY, 8, 2);
    630697        /* Enable FIFO, clear them, with 14-byte threshold. */
    631         pio_write_8(port + 2, 0xC7);
     698        pio_write_8(&ns->regs->iid, NS8250_FCR_FIFOENABLE
     699            | NS8250_FCR_RXFIFORESET | NS8250_FCR_TXFIFORESET
     700            | NS8250_FCR_RXTRIGGERLOW | NS8250_FCR_RXTRIGGERHI);
    632701        /*
    633702         * RTS/DSR set (Request to Send and Data Terminal Ready lines enabled),
    634703         * Aux Output2 set - needed for interrupts.
    635704         */
    636         pio_write_8(port + 4, 0x0B);
     705        pio_write_8(&ns->regs->mcr, NS8250_MCR_DTR | NS8250_MCR_RTS
     706            | NS8250_MCR_OUT2);
    637707}
    638708
    … …  
    644714{
    645715        /* Disable FIFO */
    646         pio_write_8(ns->port + 2, 0x00);
     716        pio_write_8(&ns->regs->iid, 0x00);
    647717        /* Disable DTR, RTS, OUT1, OUT2 (int. enable) */
    648         pio_write_8(ns->port + 4, 0x00);
     718        pio_write_8(&ns->regs->mcr, 0x00);
    649719        /* Disable all interrupts from the port */
    650         ns8250_port_interrupts_disable(ns->port);
     720        ns8250_port_interrupts_disable(ns->regs);
    651721}
    652722
    … …  
    658728static void ns8250_read_from_device(ns8250_t *ns)
    659729{
    660         ioport8_t *port = ns->port;
     730        ns8250_regs_t *regs = ns->regs;
    661731        bool cont = true;
    662732       
    … …  
    664734                fibril_mutex_lock(&ns->mutex);
    665735               
    666                 cont = ns8250_received(port);
     736                cont = ns8250_received(regs);
    667737                if (cont) {
    668                         uint8_t val = ns8250_read_8(port);
     738                        uint8_t val = ns8250_read_8(regs);
    669739                       
    670740                        if (ns->client_connected) {
    … …  
    896966{
    897967        ns8250_t *data = (ns8250_t *) dev->driver_data;
    898         ioport8_t *port = data->port;
     968        ns8250_regs_t *regs = data->regs;
    899969       
    900970        fibril_mutex_lock(&data->mutex);
    901         ns8250_port_interrupts_disable(port);
    902         *baud_rate = ns8250_port_get_baud_rate(port);
    903         ns8250_port_get_com_props(port, parity, word_length, stop_bits);
    904         ns8250_port_interrupts_enable(port);
     971        ns8250_port_interrupts_disable(regs);
     972        *baud_rate = ns8250_port_get_baud_rate(regs);
     973        ns8250_port_get_com_props(regs, parity, word_length, stop_bits);
     974        ns8250_port_interrupts_enable(regs);
    905975        fibril_mutex_unlock(&data->mutex);
    906976       
    … …  
    927997       
    928998        ns8250_t *data = (ns8250_t *) dev->driver_data;
    929         ioport8_t *port = data->port;
     999        ns8250_regs_t *regs = data->regs;
    9301000        int ret;
    9311001       
    9321002        fibril_mutex_lock(&data->mutex);
    933         ns8250_port_interrupts_disable(port);
    934         ret = ns8250_port_set_baud_rate(port, baud_rate);
     1003        ns8250_port_interrupts_disable(regs);
     1004        ret = ns8250_port_set_baud_rate(regs, baud_rate);
    9351005        if (ret == EOK)
    936                 ret = ns8250_port_set_com_props(port, parity, word_length, stop_bits);
    937         ns8250_port_interrupts_enable(port);
     1006                ret = ns8250_port_set_com_props(regs, parity, word_length, stop_bits);
     1007        ns8250_port_interrupts_enable(regs);
    9381008        fibril_mutex_unlock(&data->mutex);
    9391009       

  • uspace/drv/char/ps2mouse/main.c

    r1b90e90 r81716eb  
    3535#include <libarch/inttypes.h>
    3636#include <ddf/driver.h>
    37 #include <devman.h>
    3837#include <device/hw_res_parsed.h>
    3938#include <errno.h>

  • uspace/drv/char/xtkbd/main.c

    r1b90e90 r81716eb  
    3535#include <libarch/inttypes.h>
    3636#include <ddf/driver.h>
    37 #include <devman.h>
    3837#include <device/hw_res_parsed.h>
    3938#include <errno.h>

  • uspace/drv/infrastructure/root/root.c

    r1b90e90 r81716eb  
    5353#include <ddf/driver.h>
    5454#include <ddf/log.h>
    55 #include <devman.h>
    56 #include <ipc/devman.h>
    5755
    5856#define NAME "root"

  • uspace/drv/infrastructure/rootpc/rootpc.c

    r1b90e90 r81716eb  
    4848#include <ddf/driver.h>
    4949#include <ddf/log.h>
    50 #include <devman.h>
    51 #include <ipc/devman.h>
    5250#include <ipc/dev_iface.h>
    5351#include <ops/hw_res.h>

  • uspace/drv/nic/e1k/e1k.c

    r1b90e90 r81716eb  
    4646#include <ddf/log.h>
    4747#include <ddf/interrupt.h>
    48 #include <devman.h>
    4948#include <device/hw_res_parsed.h>
    5049#include <device/pci.h>
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