Changeset 7f1c620 in mainline for arch/amd64


Ignore:
Timestamp:
2006-07-04T17:17:56Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
0ffa3ef5
Parents:
991779c5
Message:

Replace old u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).

Location:
arch/amd64
Files:
24 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/include/asm.h

    r991779c5 r7f1c620  
    4040#include <config.h>
    4141
    42 extern void asm_delay_loop(__u32 t);
    43 extern void asm_fake_loop(__u32 t);
     42extern void asm_delay_loop(uint32_t t);
     43extern void asm_fake_loop(uint32_t t);
    4444
    4545/** Return base address of current stack.
    … …  
    4949 * The stack must start on page boundary.
    5050 */
    51 static inline __address get_stack_base(void)
    52 {
    53         __address v;
     51static inline uintptr_t get_stack_base(void)
     52{
     53        uintptr_t v;
    5454       
    55         __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
     55        __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
    5656       
    5757        return v;
    … …  
    6969 * @return Value read
    7070 */
    71 static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
     71static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
    7272
    7373/** Byte to port
    … …  
    7878 * @param val Value to write
    7979 */
    80 static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
     80static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
    8181
    8282/** Swap Hidden part of GS register with visible one */
    … …  
    150150
    151151/** Write to MSR */
    152 static inline void write_msr(__u32 msr, __u64 value)
     152static inline void write_msr(uint32_t msr, uint64_t value)
    153153{
    154154        __asm__ volatile (
    155155                "wrmsr;" : : "c" (msr),
    156                 "a" ((__u32)(value)),
    157                 "d" ((__u32)(value >> 32))
    158                 );
    159 }
    160 
    161 static inline __native read_msr(__u32 msr)
    162 {
    163         __u32 ax, dx;
     156                "a" ((uint32_t)(value)),
     157                "d" ((uint32_t)(value >> 32))
     158                );
     159}
     160
     161static inline unative_t read_msr(uint32_t msr)
     162{
     163        uint32_t ax, dx;
    164164
    165165        __asm__ volatile (
    166166                "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
    167167                );
    168         return ((__u64)dx << 32) | ax;
     168        return ((uint64_t)dx << 32) | ax;
    169169}
    170170
    … …  
    188188}
    189189
    190 static inline __address * get_ip()
    191 {
    192         __address *ip;
     190static inline uintptr_t * get_ip()
     191{
     192        uintptr_t *ip;
    193193
    194194        __asm__ volatile (
    … …  
    203203 * @param addr Address on a page whose TLB entry is to be invalidated.
    204204 */
    205 static inline void invlpg(__address addr)
    206 {
    207         __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
     205static inline void invlpg(uintptr_t addr)
     206{
     207        __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
    208208}
    209209
    … …  
    239239 * @param sel Selector specifying descriptor of TSS segment.
    240240 */
    241 static inline void tr_load(__u16 sel)
     241static inline void tr_load(uint16_t sel)
    242242{
    243243        __asm__ volatile ("ltr %0" : : "r" (sel));
    244244}
    245245
    246 #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
     246#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
    247247    { \
    248         __native res; \
     248        unative_t res; \
    249249        __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
    250250        return res; \
    251251    }
    252252
    253 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
     253#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
    254254    { \
    255255        __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \

  • arch/amd64/include/atomic.h

    r991779c5 r7f1c620  
    8484#define atomic_predec(val) (atomic_postdec(val)-1)
    8585
    86 static inline __u64 test_and_set(atomic_t *val) {
    87         __u64 v;
     86static inline uint64_t test_and_set(atomic_t *val) {
     87        uint64_t v;
    8888       
    8989        __asm__ volatile (
    … …  
    100100static inline void atomic_lock_arch(atomic_t *val)
    101101{
    102         __u64 tmp;
     102        uint64_t tmp;
    103103
    104104        preemption_disable();

  • arch/amd64/include/byteorder.h

    r991779c5 r7f1c620  
    3737
    3838/* AMD64 is little-endian */
    39 #define __native_le2host(n)             (n)
    40 #define __u64_le2host(n)                (n)
     39#define unative_t_le2host(n)            (n)
     40#define uint64_t_le2host(n)             (n)
    4141
    4242#endif

  • arch/amd64/include/context.h

    r991779c5 r7f1c620  
    5151 */
    5252struct context {
    53     __address sp;
    54     __address pc;
     53    uintptr_t sp;
     54    uintptr_t pc;
    5555   
    56     __u64 rbx;
    57     __u64 rbp;
     56    uint64_t rbx;
     57    uint64_t rbp;
    5858
    59     __u64 r12;
    60     __u64 r13;
    61     __u64 r14;
    62     __u64 r15;
     59    uint64_t r12;
     60    uint64_t r13;
     61    uint64_t r14;
     62    uint64_t r15;
    6363
    6464    ipl_t ipl;

  • arch/amd64/include/cpu.h

    r991779c5 r7f1c620  
    7777
    7878extern void set_efer_flag(int flag);
    79 extern __u64 read_efer_flag(void);
     79extern uint64_t read_efer_flag(void);
    8080void cpu_setup_fpu(void);
    8181

  • arch/amd64/include/cpuid.h

    r991779c5 r7f1c620  
    4848
    4949struct cpu_info {
    50         __u32 cpuid_eax;
    51         __u32 cpuid_ebx;
    52         __u32 cpuid_ecx;
    53         __u32 cpuid_edx;
     50        uint32_t cpuid_eax;
     51        uint32_t cpuid_ebx;
     52        uint32_t cpuid_ecx;
     53        uint32_t cpuid_edx;
    5454} __attribute__ ((packed));
    5555
    5656extern int has_cpuid(void);
    5757
    58 extern void cpuid(__u32 cmd, cpu_info_t *info);
     58extern void cpuid(uint32_t cmd, cpu_info_t *info);
    5959
    6060
    61 extern __u64 rdtsc(void);
     61extern uint64_t rdtsc(void);
    6262
    6363#endif /* __ASM__ */

  • arch/amd64/include/faddr.h

    r991779c5 r7f1c620  
    2727 */
    2828
    29  /** @addtogroup amd64 
     29/** @addtogroup amd64   
    3030 * @{
    3131 */
    … …  
    3838#include <arch/types.h>
    3939
    40 #define FADDR(fptr)             ((__address) (fptr))
     40#define FADDR(fptr)             ((uintptr_t) (fptr))
    4141
    4242#endif
    4343
    44  /** @}
     44/** @}
    4545 */
    46 

  • arch/amd64/include/interrupt.h

    r991779c5 r7f1c620  
    7171/** This is passed to interrupt handlers */
    7272struct istate {
    73         __u64 rax;
    74         __u64 rbx;
    75         __u64 rcx;
    76         __u64 rdx;
    77         __u64 rsi;
    78         __u64 rdi;
    79         __u64 r8;
    80         __u64 r9;
    81         __u64 r10;
    82         __u64 r11;
    83         __u64 r12;
    84         __u64 r13;
    85         __u64 r14;
    86         __u64 r15;
    87         __u64 rbp;
    88         __u64 error_word;
    89         __u64 rip;
    90         __u64 cs;
    91         __u64 rflags;
    92         __u64 stack[]; /* Additional data on stack */
     73        uint64_t rax;
     74        uint64_t rbx;
     75        uint64_t rcx;
     76        uint64_t rdx;
     77        uint64_t rsi;
     78        uint64_t rdi;
     79        uint64_t r8;
     80        uint64_t r9;
     81        uint64_t r10;
     82        uint64_t r11;
     83        uint64_t r12;
     84        uint64_t r13;
     85        uint64_t r14;
     86        uint64_t r15;
     87        uint64_t rbp;
     88        uint64_t error_word;
     89        uint64_t rip;
     90        uint64_t cs;
     91        uint64_t rflags;
     92        uint64_t stack[]; /* Additional data on stack */
    9393};
    9494
    … …  
    9999}
    100100
    101 static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
     101static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
    102102{
    103103        istate->rip = retaddr;
    104104}
    105 static inline __native istate_get_pc(istate_t *istate)
     105static inline unative_t istate_get_pc(istate_t *istate)
    106106{
    107107        return istate->rip;
    108108}
    109109
    110 extern void (* disable_irqs_function)(__u16 irqmask);
    111 extern void (* enable_irqs_function)(__u16 irqmask);
     110extern void (* disable_irqs_function)(uint16_t irqmask);
     111extern void (* enable_irqs_function)(uint16_t irqmask);
    112112extern void (* eoi_function)(void);
    113113
    … …  
    121121extern void tlb_shootdown_ipi(int n, istate_t *istate);
    122122
    123 extern void trap_virtual_enable_irqs(__u16 irqmask);
    124 extern void trap_virtual_disable_irqs(__u16 irqmask);
     123extern void trap_virtual_enable_irqs(uint16_t irqmask);
     124extern void trap_virtual_disable_irqs(uint16_t irqmask);
    125125extern void trap_virtual_eoi(void);
    126126/* AMD64 - specific page handler */

  • arch/amd64/include/memstr.h

    r991779c5 r7f1c620  
    5050static inline void * memcpy(void * dst, const void * src, size_t cnt)
    5151{
    52         __native d0, d1, d2;
     52        unative_t d0, d1, d2;
    5353
    5454        __asm__ __volatile__(
    … …  
    6060                "1:\n"
    6161                : "=&c" (d0), "=&D" (d1), "=&S" (d2)
    62                 : "0" ((__native)(cnt / 8)), "g" ((__native)cnt), "1" ((__native) dst), "2" ((__native) src)
     62                : "0" ((unative_t)(cnt / 8)), "g" ((unative_t)cnt), "1" ((unative_t) dst), "2" ((unative_t) src)
    6363                : "memory");
    6464
    … …  
    8080static inline int memcmp(const void * src, const void * dst, size_t cnt)
    8181{
    82         __native d0, d1, d2;
    83         __native ret;
     82        unative_t d0, d1, d2;
     83        unative_t ret;
    8484       
    8585        __asm__ (
    … …  
    9090                "1:\n"
    9191                : "=a" (ret), "=%S" (d0), "=&D" (d1), "=&c" (d2)
    92                 : "0" (0), "1" (src), "2" (dst), "3" ((__native)cnt)
     92                : "0" (0), "1" (src), "2" (dst), "3" ((unative_t)cnt)
    9393        );
    9494       
    … …  
    105105 * @param x Value to fill
    106106 */
    107 static inline void memsetw(__address dst, size_t cnt, __u16 x)
     107static inline void memsetw(uintptr_t dst, size_t cnt, uint16_t x)
    108108{
    109         __native d0, d1;
     109        unative_t d0, d1;
    110110       
    111111        __asm__ __volatile__ (
    112112                "rep stosw\n\t"
    113113                : "=&D" (d0), "=&c" (d1), "=a" (x)
    114                 : "0" (dst), "1" ((__native)cnt), "2" (x)
     114                : "0" (dst), "1" ((unative_t)cnt), "2" (x)
    115115                : "memory"
    116116        );
    … …  
    127127 * @param x Value to fill
    128128 */
    129 static inline void memsetb(__address dst, size_t cnt, __u8 x)
     129static inline void memsetb(uintptr_t dst, size_t cnt, uint8_t x)
    130130{
    131         __native d0, d1;
     131        unative_t d0, d1;
    132132       
    133133        __asm__ __volatile__ (
    134134                "rep stosb\n\t"
    135135                : "=&D" (d0), "=&c" (d1), "=a" (x)
    136                 : "0" (dst), "1" ((__native)cnt), "2" (x)
     136                : "0" (dst), "1" ((unative_t)cnt), "2" (x)
    137137                : "memory"
    138138        );

  • arch/amd64/include/mm/frame.h

    r991779c5 r7f1c620  
    4545
    4646#ifndef __ASM__
    47 extern __address last_frame;
     47extern uintptr_t last_frame;
    4848extern void frame_arch_init(void);
    4949#endif /* __ASM__ */

  • arch/amd64/include/mm/page.h

    r991779c5 r7f1c620  
    2727 */
    2828
    29  /** @addtogroup amd64mm       
     29/** @addtogroup amd64mm
    3030 * @{
    3131 */
    … …  
    6161
    6262#ifndef __ASM__
    63 static inline __address ka2pa(__address x)
     63static inline uintptr_t ka2pa(uintptr_t x)
    6464{
    6565        if (x > 0xffffffff80000000)
    … …  
    6868                return x - 0xffff800000000000;
    6969}
    70 # define KA2PA(x)      ka2pa((__address)x)
    71 # define PA2KA_CODE(x)      (((__address) (x)) + 0xffffffff80000000)
    72 # define PA2KA(x)      (((__address) (x)) + 0xffff800000000000)
     70# define KA2PA(x)      ka2pa((uintptr_t)x)
     71# define PA2KA_CODE(x)      (((uintptr_t) (x)) + 0xffffffff80000000)
     72# define PA2KA(x)      (((uintptr_t) (x)) + 0xffff800000000000)
    7373#else
    7474# define KA2PA(x)      ((x) - 0xffffffff80000000)
    … …  
    8686#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>12)&0x1ff)
    8787
    88 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) ((((__u64) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
    89 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          ((pte_t *) ((((__u64) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
    90 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          ((pte_t *) ((((__u64) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
    91 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((__address *) ((((__u64) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
    92 
    93 #define SET_PTL0_ADDRESS_ARCH(ptl0)             (write_cr3((__address) (ptl0)))
     88#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
     89#define GET_PTL2_ADDRESS_ARCH(ptl1, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
     90#define GET_PTL3_ADDRESS_ARCH(ptl2, i)          ((pte_t *) ((((uint64_t) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
     91#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((uintptr_t *) ((((uint64_t) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
     92
     93#define SET_PTL0_ADDRESS_ARCH(ptl0)             (write_cr3((uintptr_t) (ptl0)))
    9494#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
    9595#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)       set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
    … …  
    107107#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
    108108
    109 #define PTE_VALID_ARCH(p)                       (*((__u64 *) (p)) != 0)
     109#define PTE_VALID_ARCH(p)                       (*((uint64_t *) (p)) != 0)
    110110#define PTE_PRESENT_ARCH(p)                     ((p)->present != 0)
    111 #define PTE_GET_FRAME_ARCH(p)                   ((((__address)(p)->addr_12_31)<<12) | ((__address)(p)->addr_32_51<<32))
     111#define PTE_GET_FRAME_ARCH(p)                   ((((uintptr_t)(p)->addr_12_31)<<12) | ((uintptr_t)(p)->addr_32_51<<32))
    112112#define PTE_WRITABLE_ARCH(p)                    ((p)->writeable != 0)
    113113#define PTE_EXECUTABLE_ARCH(p)                  ((p)->no_execute == 0)
    … …  
    165165}
    166166
    167 static inline void set_pt_addr(pte_t *pt, index_t i, __address a)
     167static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a)
    168168{
    169169        pte_t *p = &pt[i];
    … …  
    198198#endif
    199199
    200  /** @}
    201  */
    202 
     200/** @}
     201 */

  • arch/amd64/include/pm.h

    r991779c5 r7f1c620  
    141141
    142142struct ptr_16_64 {
    143         __u16 limit;
    144         __u64 base;
     143        uint16_t limit;
     144        uint64_t base;
    145145} __attribute__ ((packed));
    146146typedef struct ptr_16_64 ptr_16_64_t;
    147147
    148148struct ptr_16_32 {
    149         __u16 limit;
    150         __u32 base;
     149        uint16_t limit;
     150        uint32_t base;
    151151} __attribute__ ((packed));
    152152typedef struct ptr_16_32 ptr_16_32_t;
    153153
    154154struct tss {
    155         __u32 reserve1;
    156         __u64 rsp0;
    157         __u64 rsp1;
    158         __u64 rsp2;
    159         __u64 reserve2;
    160         __u64 ist1;
    161         __u64 ist2;
    162         __u64 ist3;
    163         __u64 ist4;
    164         __u64 ist5;
    165         __u64 ist6;
    166         __u64 ist7;
    167         __u64 reserve3;
    168         __u16 reserve4;
    169         __u16 iomap_base;
    170         __u8 iomap[TSS_IOMAP_SIZE];
     155        uint32_t reserve1;
     156        uint64_t rsp0;
     157        uint64_t rsp1;
     158        uint64_t rsp2;
     159        uint64_t reserve2;
     160        uint64_t ist1;
     161        uint64_t ist2;
     162        uint64_t ist3;
     163        uint64_t ist4;
     164        uint64_t ist5;
     165        uint64_t ist6;
     166        uint64_t ist7;
     167        uint64_t reserve3;
     168        uint16_t reserve4;
     169        uint16_t iomap_base;
     170        uint8_t iomap[TSS_IOMAP_SIZE];
    171171} __attribute__ ((packed));
    172172typedef struct tss tss_t;
    … …  
    183183extern void pm_init(void);
    184184
    185 extern void gdt_tss_setbase(descriptor_t *d, __address base);
    186 extern void gdt_tss_setlimit(descriptor_t *d, __u32 limit);
     185extern void gdt_tss_setbase(descriptor_t *d, uintptr_t base);
     186extern void gdt_tss_setlimit(descriptor_t *d, uint32_t limit);
    187187
    188188extern void idt_init(void);
    189 extern void idt_setoffset(idescriptor_t *d, __address offset);
     189extern void idt_setoffset(idescriptor_t *d, uintptr_t offset);
    190190
    191191extern void tss_initialize(tss_t *t);

  • arch/amd64/include/proc/thread.h

    r991779c5 r7f1c620  
    3939
    4040typedef struct {
    41         __native tls;
     41        unative_t tls;
    4242} thread_arch_t;
    4343

  • arch/amd64/include/types.h

    r991779c5 r7f1c620  
    2727 */
    2828
    29  /** @addtogroup amd64 
     29/** @addtogroup amd64   
    3030 * @{
    3131 */
    … …  
    3838#define NULL 0
    3939
    40 typedef signed char __s8;
    41 typedef signed short __s16;
    42 typedef signed int __s32;
    43 typedef signed long long __s64;
     40typedef signed char int8_t;
     41typedef signed short int16_t;
     42typedef signed int int32_t;
     43typedef signed long long int64_t;
    4444
    45 typedef unsigned char __u8;
    46 typedef unsigned short __u16;
    47 typedef unsigned int __u32;
    48 typedef unsigned long long __u64;
     45typedef unsigned char uint8_t;
     46typedef unsigned short uint16_t;
     47typedef unsigned int uint32_t;
     48typedef unsigned long long uint64_t;
    4949
    50 typedef __u64 __address;
    51 typedef __u64 pfn_t;
     50typedef uint64_t uintptr_t;
     51typedef uint64_t pfn_t;
    5252
    5353/* Flags of processor (return value of interrupts_disable()) */
    54 typedef __u64 ipl_t;
     54typedef uint64_t ipl_t;
    5555
    56 typedef __u64 __native;
    57 typedef __s64 __snative;
     56typedef uint64_t unative_t;
     57typedef int64_t native_t;
    5858
    5959typedef struct page_specifier pte_t;
    … …  
    6161#endif
    6262
    63  /** @}
     63/** @}
    6464 */
    65 

  • arch/amd64/src/amd64.c

    r991779c5 r7f1c620  
    187187 * we need not to go to CPL0 to read it.
    188188 */
    189 __native sys_tls_set(__native addr)
     189unative_t sys_tls_set(unative_t addr)
    190190{
    191191        THREAD->arch.tls = addr;

  • arch/amd64/src/cpu/cpu.c

    r991779c5 r7f1c620  
    125125{
    126126        CPU->arch.tss = tss_p;
    127         CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
     127        CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
    128128        CPU->fpu_owner = NULL;
    129129}

  • arch/amd64/src/ddi/ddi.c

    r991779c5 r7f1c620  
    5656 * @return 0 on success or an error code from errno.h.
    5757 */
    58 int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
     58int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
    5959{
    6060        count_t bits;
    … …  
    6666        if (task->arch.iomap.bits < bits) {
    6767                bitmap_t oldiomap;
    68                 __u8 *newmap;
     68                uint8_t *newmap;
    6969       
    7070                /*
    … …  
    7272                 */
    7373               
    74                 newmap = (__u8 *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
     74                newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
    7575                if (!newmap)
    7676                        return ENOMEM;

  • arch/amd64/src/debugger.c

    r991779c5 r7f1c620  
    4747
    4848typedef struct  {
    49         __address address;      /**< Breakpoint address */
     49        uintptr_t address;      /**< Breakpoint address */
    5050        int flags;              /**< Flags regarding breakpoint */
    5151        int counter;            /**< How many times the exception occured */
    … …  
    123123static void setup_dr(int curidx)
    124124{
    125         __native dr7;
     125        unative_t dr7;
    126126        bpinfo_t *cur = &breakpoints[curidx];
    127127        int flags = breakpoints[curidx].flags;
    … …  
    154154                } else {
    155155                        if (sizeof(int) == 4)
    156                                 dr7 |= ((__native) 0x3) << (18 + 4*curidx);
     156                                dr7 |= ((unative_t) 0x3) << (18 + 4*curidx);
    157157                        else /* 8 */
    158                                 dr7 |= ((__native) 0x2) << (18 + 4*curidx);
     158                                dr7 |= ((unative_t) 0x2) << (18 + 4*curidx);
    159159                       
    160160                        if ((flags & BKPOINT_WRITE))
    161                                 dr7 |= ((__native) 0x1) << (16 + 4*curidx);
     161                                dr7 |= ((unative_t) 0x1) << (16 + 4*curidx);
    162162                        else if ((flags & BKPOINT_READ_WRITE))
    163                                 dr7 |= ((__native) 0x3) << (16 + 4*curidx);
     163                                dr7 |= ((unative_t) 0x3) << (16 + 4*curidx);
    164164                }
    165165
    … …  
    206206        cur = &breakpoints[curidx];
    207207
    208         cur->address = (__address) where;
     208        cur->address = (uintptr_t) where;
    209209        cur->flags = flags;
    210210        cur->counter = 0;
    … …  
    236236        if (! (breakpoints[slot].flags & BKPOINT_INSTR)) {
    237237                if ((breakpoints[slot].flags & BKPOINT_CHECK_ZERO)) {
    238                         if (*((__native *) breakpoints[slot].address) != 0)
     238                        if (*((unative_t *) breakpoints[slot].address) != 0)
    239239                                return;
    240240                        printf("**** Found ZERO on address %p ****\n",
    … …  
    242242                } else {
    243243                        printf("Data watchpoint - new data: %p\n",
    244                                *((__native *) breakpoints[slot].address));
     244                               *((unative_t *) breakpoints[slot].address));
    245245                }
    246246        }
    … …  
    316316static void debug_exception(int n, istate_t *istate)
    317317{
    318         __native dr6;
     318        unative_t dr6;
    319319        int i;
    320320       

  • arch/amd64/src/interrupt.c

    r991779c5 r7f1c620  
    5757{
    5858        char *symbol;
    59 /*      __u64 *x = &istate->stack[0]; */
     59/*      uint64_t *x = &istate->stack[0]; */
    6060
    6161        if (!(symbol=get_symtab_entry(istate->rip)))
    … …  
    8080 */
    8181
    82 void (* disable_irqs_function)(__u16 irqmask) = NULL;
    83 void (* enable_irqs_function)(__u16 irqmask) = NULL;
     82void (* disable_irqs_function)(uint16_t irqmask) = NULL;
     83void (* enable_irqs_function)(uint16_t irqmask) = NULL;
    8484void (* eoi_function)(void) = NULL;
    8585
    … …  
    142142}
    143143
    144 void trap_virtual_enable_irqs(__u16 irqmask)
     144void trap_virtual_enable_irqs(uint16_t irqmask)
    145145{
    146146        if (enable_irqs_function)
    … …  
    150150}
    151151
    152 void trap_virtual_disable_irqs(__u16 irqmask)
     152void trap_virtual_disable_irqs(uint16_t irqmask)
    153153{
    154154        if (disable_irqs_function)
    … …  
    175175
    176176/* Reregister irq to be IPC-ready */
    177 void irq_ipc_bind_arch(__native irq)
     177void irq_ipc_bind_arch(unative_t irq)
    178178{
    179179        if (irq == IRQ_CLK)

  • arch/amd64/src/mm/memory_init.c

    r991779c5 r7f1c620  
    3838#include <print.h>
    3939
    40 __u8 e820counter = 0xff;
     40uint8_t e820counter = 0xff;
    4141struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS];
    42 __u32 e801memorysize;
     42uint32_t e801memorysize;
    4343
    4444size_t get_memory_size(void)
    … …  
    4949void memory_print_map(void)
    5050{
    51         __u8 i;
     51        uint8_t i;
    5252       
    5353        for (i=0;i<e820counter;i++) {

  • arch/amd64/src/mm/page.c

    r991779c5 r7f1c620  
    6363
    6464#define SETUP_PTL1(ptl0, page, tgt)  {  \
    65         SET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
     65        SET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    6666        SET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    6767    }
    6868#define SETUP_PTL2(ptl1, page, tgt)  {  \
    69         SET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
     69        SET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    7070        SET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    7171    }
    7272#define SETUP_PTL3(ptl2, page, tgt)  {  \
    73         SET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
     73        SET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    7474        SET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    7575    }
    7676#define SETUP_FRAME(ptl3, page, tgt)  { \
    77         SET_FRAME_ADDRESS_ARCH(ptl3, PTL3_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
     77        SET_FRAME_ADDRESS_ARCH(ptl3, PTL3_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    7878        SET_FRAME_FLAGS_ARCH(ptl3, PTL3_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    7979    }
    … …  
    8282void page_arch_init(void)
    8383{
    84         __address cur;
     84        uintptr_t cur;
    8585        int i;
    8686        int identity_flags = PAGE_CACHEABLE | PAGE_EXEC | PAGE_GLOBAL;
    … …  
    110110
    111111                exc_register(14, "page_fault", (iroutine)page_fault);
    112                 write_cr3((__address) AS_KERNEL->page_table);
    113         }
    114         else {
    115                 write_cr3((__address) AS_KERNEL->page_table);
     112                write_cr3((uintptr_t) AS_KERNEL->page_table);
     113        }
     114        else {
     115                write_cr3((uintptr_t) AS_KERNEL->page_table);
    116116        }
    117117}
    … …  
    126126void ident_page_fault(int n, istate_t *istate)
    127127{
    128         __address page;
    129         static __address oldpage = 0;
     128        uintptr_t page;
     129        static uintptr_t oldpage = 0;
    130130        pte_t *aptl_1, *aptl_2, *aptl_3;
    131131
    … …  
    174174void page_fault(int n, istate_t *istate)
    175175{
    176         __address page;
     176        uintptr_t page;
    177177        pf_access_t access;
    178178       
    … …  
    199199
    200200
    201 __address hw_map(__address physaddr, size_t size)
     201uintptr_t hw_map(uintptr_t physaddr, size_t size)
    202202{
    203203        if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
    204204                panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
    205205       
    206         __address virtaddr = PA2KA(last_frame);
     206        uintptr_t virtaddr = PA2KA(last_frame);
    207207        pfn_t i;
    208208        for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)

  • arch/amd64/src/pm.c

    r991779c5 r7f1c620  
    124124idescriptor_t idt[IDT_ITEMS];
    125125
    126 ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
    127 ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
     126ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };
     127ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };
    128128
    129129static tss_t tss;
    130130tss_t *tss_p = NULL;
    131131
    132 void gdt_tss_setbase(descriptor_t *d, __address base)
     132void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
    133133{
    134134        tss_descriptor_t *td = (tss_descriptor_t *) d;
    … …  
    140140}
    141141
    142 void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
     142void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
    143143{
    144144        struct tss_descriptor *td = (tss_descriptor_t *) d;
    … …  
    148148}
    149149
    150 void idt_setoffset(idescriptor_t *d, __address offset)
     150void idt_setoffset(idescriptor_t *d, uintptr_t offset)
    151151{
    152152        /*
    … …  
    160160void tss_initialize(tss_t *t)
    161161{
    162         memsetb((__address) t, sizeof(tss_t), 0);
     162        memsetb((uintptr_t) t, sizeof(tss_t), 0);
    163163}
    164164
    … …  
    180180                d->type = AR_INTERRUPT; /* masking interrupt */
    181181
    182                 idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
     182                idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
    183183                exc_register(i, "undef", (iroutine)null_interrupt);
    184184        }
    … …  
    215215                 * non boot-mapped pointer, initialize the CR3 register
    216216                 * ahead of page_init */
    217                 write_cr3((__address) AS_KERNEL->page_table);
     217                write_cr3((uintptr_t) AS_KERNEL->page_table);
    218218
    219219                tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
    … …  
    229229        tss_desc->dpl = PL_KERNEL;
    230230       
    231         gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
     231        gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
    232232        gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
    233233

  • arch/amd64/src/proc/scheduler.c

    r991779c5 r7f1c620  
    5757void before_thread_runs_arch(void)
    5858{
    59         CPU->arch.tss->rsp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
     59        CPU->arch.tss->rsp0 = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
    6060
    6161        /* Syscall support - write address of thread stack pointer to
    6262         * hidden part of gs */
    6363        swapgs();
    64         write_msr(AMD_MSR_GS, (__u64)&THREAD->kstack);
     64        write_msr(AMD_MSR_GS, (uint64_t)&THREAD->kstack);
    6565        swapgs();
    6666

  • arch/amd64/src/syscall.c

    r991779c5 r7f1c620  
    5858         */
    5959        write_msr(AMD_MSR_STAR,
    60                   ((__u64)(gdtselector(KDATA_DES) | PL_USER)<<48) \
    61                   | ((__u64)(gdtselector(KTEXT_DES) | PL_KERNEL)<<32));
    62         write_msr(AMD_MSR_LSTAR, (__u64)syscall_entry);
     60                  ((uint64_t)(gdtselector(KDATA_DES) | PL_USER)<<48) \
     61                  | ((uint64_t)(gdtselector(KTEXT_DES) | PL_KERNEL)<<32));
     62        write_msr(AMD_MSR_LSTAR, (uint64_t)syscall_entry);
    6363        /* Mask RFLAGS on syscall
    6464         * - disable interrupts, until we exchange the stack register
Note: See TracChangeset for help on using the changeset viewer.