Changeset 7cd7a8d in mainline for kernel/arch/ia64/include

Timestamp:

2018-08-02T20:38:05Z (7 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9b7adc38

Parents:

0c27956

git-author:

Jakub Jermar <jakub@…> (2018-08-01 22:48:10)

git-committer:

Jakub Jermar <jakub@…> (2018-08-02 20:38:05)

Message:

Preserve AR.FPSR in thread context

AR.FPSR is a preserved register so it should be part of the thread
context, leaving its extra copy in istate_t rather for debugging
purposes.

In this commit we also disable all IEEE FP traps and the
Denormal/Unnormal Operand Floating-Point Exception fault for each new
thread context, leaving the thread with the possibility to change this
setting later in uspace.

Location:

kernel/arch/ia64/include/arch

Files:

• context.h (modified) (1 diff)
• context_struct.h (modified) (3 diffs)
• register.h (modified) (1 diff)

kernel/arch/ia64/include/arch/context.h

@@ -57 +57 @@
                 (c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size / 2), REGISTER_STACK_ALIGNMENT); \
                 (c)->ar_pfs &= PFM_MASK; \
+                (c)->ar_fpsr = FPSR_TRAPS_ALL; \
                 (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size / 2), STACK_ALIGNMENT) - SP_DELTA; \
                 (c)->r1 = (uintptr_t) &__gp; \

kernel/arch/ia64/include/arch/context_struct.h

@@ -37 +37 @@
 #define CONTEXT_OFFSET_AR_RNAT         0x28
 #define CONTEXT_OFFSET_AR_LC           0x30
-#define CONTEXT_OFFSET_R1              0x38
-#define CONTEXT_OFFSET_R4              0x40
-#define CONTEXT_OFFSET_R5              0x48
-#define CONTEXT_OFFSET_R6              0x50
-#define CONTEXT_OFFSET_R7              0x58
-#define CONTEXT_OFFSET_SP              0x60
-#define CONTEXT_OFFSET_R13             0x68
-#define CONTEXT_OFFSET_PC              0x70
-#define CONTEXT_OFFSET_B1              0x78
-#define CONTEXT_OFFSET_B2              0x80
-#define CONTEXT_OFFSET_B3              0x88
-#define CONTEXT_OFFSET_B4              0x90
-#define CONTEXT_OFFSET_B5              0x98
-#define CONTEXT_OFFSET_PR              0xa0
+#define CONTEXT_OFFSET_AR_FPSR         0x38
+#define CONTEXT_OFFSET_R1              0x40
+#define CONTEXT_OFFSET_R4              0x48
+#define CONTEXT_OFFSET_R5              0x50
+#define CONTEXT_OFFSET_R6              0x58
+#define CONTEXT_OFFSET_R7              0x60
+#define CONTEXT_OFFSET_SP              0x68
+#define CONTEXT_OFFSET_R13             0x70
+#define CONTEXT_OFFSET_PC              0x78
+#define CONTEXT_OFFSET_B1              0x80
+#define CONTEXT_OFFSET_B2              0x88
+#define CONTEXT_OFFSET_B3              0x90
+#define CONTEXT_OFFSET_B4              0x98
+#define CONTEXT_OFFSET_B5              0xa0
+#define CONTEXT_OFFSET_PR              0xa8
 #define CONTEXT_OFFSET_F2              0xb0
 #define CONTEXT_OFFSET_F3              0xc0
@@ -89 +90 @@
         uint64_t ar_rnat;
         uint64_t ar_lc;
+        uint64_t ar_fpsr;
 
         // General registers.
@@ -111 +113 @@
         // Predicate registers.
         uint64_t pr;
+
+        // Floating-point registers.
         uint128_t f2;
         uint128_t f3;

kernel/arch/ia64/include/arch/register.h

@@ -68 +68 @@
 #define RSC_MODE_MASK   3
 #define RSC_PL_MASK     12
+
+#define FPSR_TRAPS_VD  (1 << 0)
+#define FPSR_TRAPS_DD  (1 << 1)
+#define FPSR_TRAPS_ZD  (1 << 2)
+#define FPSR_TRAPS_OD  (1 << 3)
+#define FPSR_TRAPS_UD  (1 << 4)
+#define FPSR_TRAPS_ID  (1 << 5)
+
+#define FPSR_TRAPS_ALL (FPSR_TRAPS_VD | FPSR_TRAPS_DD | FPSR_TRAPS_ZD | \
+    FPSR_TRAPS_OD | FPSR_TRAPS_UD | FPSR_TRAPS_ID)
 
 /** Application registers. */