Changeset 7c3fb9b in mainline for kernel/arch/arm32/src

Timestamp:

2018-05-17T08:29:01Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ff23ff

Parents:

fac0ac7

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)

Message:

Fix block comment formatting (ccheck).

Location:

kernel/arch/arm32/src

Files:

• cpu/cpu.c (modified) (2 diffs)
• exception.c (modified) (2 diffs)
• mach/beagleboardxm/beagleboardxm.c (modified) (2 diffs)
• mm/page_fault.c (modified) (1 diff)

kernel/arch/arm32/src/cpu/cpu.c

@@ -147 +147 @@
         /* Unaligned access is supported on armv6+ */
 #if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-        /* Enable unaligned access, RAZ/WI prior to armv6
+        /*
+         * Enable unaligned access, RAZ/WI prior to armv6
          * switchable on armv6, RAO/WI writes on armv7,
          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
-         * L.3.1 (p. 2456) */
+         * L.3.1 (p. 2456)
+         */
         control_reg |= SCTLR_UNALIGNED_EN_FLAG;
-        /* Disable alignment checks, this turns unaligned access to undefined,
-         * unless U bit is set. */
+        /*
+         * Disable alignment checks, this turns unaligned access to undefined,
+         * unless U bit is set.
+         */
         control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
-        /* Enable caching, On arm prior to armv7 there is only one level
+        /*
+         * Enable caching, On arm prior to armv7 there is only one level
          * of caches. Data cache is coherent.
          * "This means that the behavior of accesses from the same observer to
@@ -169 +174 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-        /* ICache coherency is elaborated on in barrier.h.
+        /*
+         * ICache coherency is elaborated on in barrier.h.
          * VIPT and PIPT caches need maintenance only on code modify,
          * so it should be safe for general use.

kernel/arch/arm32/src/exception.c

@@ -66 +66 @@
 static void install_handler(unsigned handler_addr, unsigned *vector)
 {
-        /* relative address (related to exc. vector) of the word
+        /*
+         * Relative address (related to exc. vector) of the word
          * where handler's address is stored
          */
@@ -72 +73 @@
             PREFETCH_OFFSET;
 
-        /* make it LDR instruction and store at exception vector */
+        /* Make it LDR instruction and store at exception vector */
         *vector = handler_address_ptr | LDR_OPCODE;
         smc_coherence(vector);
 
-        /* store handler's address */
+        /* Store handler's address */
         *(vector + EXC_VECTORS) = handler_addr;
 

kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

@@ -106 +106 @@
         omap_irc_init(beagleboard.irc_addr);
 
-        /* Initialize timer. Use timer1, because it is in WKUP power domain
-         * (always on) and has special capabilities for precise 1ms ticks */
+        /*
+         * Initialize timer. Use timer1, because it is in WKUP power domain
+         * (always on) and has special capabilities for precise 1ms ticks
+         */
         amdm37x_gpt_timer_ticks_init(&beagleboard.timer,
             AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ);
@@ -161 +163 @@
         }
         /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
-         * of ISR. DO this to avoid strange behavior. */
+         * of ISR. DO this to avoid strange behavior.
+         */
         omap_irc_irq_ack(beagleboard.irc_addr);
 }

kernel/arch/arm32/src/mm/page_fault.c

@@ -153 +153 @@
         }
 
-        /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
-         * A5.3 (PDF p. 206) */
+        /*
+         * See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
+         * A5.3 (PDF p. 206)
+         */
         static const struct {
                 uint32_t mask;