Changeset 7c3fb9b in mainline for kernel/arch/amd64/src


Ignore:
Timestamp:
2018-05-17T08:29:01Z (7 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6ff23ff
Parents:
fac0ac7
git-author:
Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)
git-committer:
Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)
Message:

Fix block comment formatting (ccheck).

Location:
kernel/arch/amd64/src
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/src/fpu_context.c

    rfac0ac7 r7c3fb9b  
    5757{
    5858        /* TODO: Zero all SSE, MMX etc. registers */
    59         /* Default value of SCR register is 0x1f80,
    60          * it masks all FPU exceptions*/
     59        /*
     60         * Default value of SCR register is 0x1f80,
     61         * it masks all FPU exceptions
     62         */
    6163        asm volatile (
    6264            "fninit\n"

  • kernel/arch/amd64/src/kseg.c

    rfac0ac7 r7c3fb9b  
    4242 * Allocate and initialize a per-CPU structure to be accessible via the
    4343 * GS_KERNEL segment register.
    44  **/
     44 */
    4545void kseg_init(void)
    4646{

  • kernel/arch/amd64/src/pm.c

    rfac0ac7 r7c3fb9b  
    268268                tss_p = &tss;
    269269        } else {
    270                 /* We are going to use malloc, which may return
     270                /*
     271                 * We are going to use malloc, which may return
    271272                 * non boot-mapped pointer, initialize the CR3 register
    272                  * ahead of page_init */
     273                 * ahead of page_init
     274                 */
    273275                write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
    274276

  • kernel/arch/amd64/src/syscall.c

    rfac0ac7 r7c3fb9b  
    5252        /* Setup syscall entry address */
    5353
    54         /* This is _mess_ - the 64-bit CS is argument + 16,
     54        /*
     55         * This is _mess_ - the 64-bit CS is argument + 16,
    5556         * the SS is argument + 8. The order is:
    5657         * +0(KDATA_DES), +8(UDATA_DES), +16(UTEXT_DES)
    … …  
    6061            ((uint64_t) (GDT_SELECTOR(KTEXT_DES) | PL_KERNEL) << 32));
    6162        write_msr(AMD_MSR_LSTAR, (uint64_t)syscall_entry);
    62         /* Mask RFLAGS on syscall
     63        /*
     64         * Mask RFLAGS on syscall
    6365         * - disable interrupts, until we exchange the stack register
    6466         *   (mask the IF bit)
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